IDT IDT54FCT162543TPAB Fast cmos 16-bit latched transceiver Datasheet

FAST CMOS
16-BIT LATCHED
TRANSCEIVER
IDT54/74FCT16543T/AT/CT/ET
IDT54/74FCT162543T/AT/CT/ET
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16543T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162543T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
The FCT16543T/AT/CT/ET and FCT162543T/AT/CT/ET
16-bit latched transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. For example, the Ato-B Enable (xCEAB) must be LOW in order to enter data from
the A port or to output data from the B port. xLEAB controls the
latch function. When xLEAB is LOW, the latches are transparent. A subsequent LOW-to-HIGH transition of xLEAB signal
puts the A latches in the storage mode. xOEAB performs output
enable function on the B port. Data flow from the B port to the
A port is similar but requires using xCEBA, xLEBA, and xOEBA
inputs. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT16543T/AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability to
allow "live insertion" of boards when used as backplane drivers.
The FCT162543T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162543T/AT/CT/ET are plug-in replacements for the
FCT16543T/AT/CT/ET and 54/74ABT16543 for on-board bus
interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OEBA
2OEBA
1CEBA
2CEBA
1LEBA
2LEBA
1OEAB
2OEAB
1CEAB
2CEAB
2LEAB
1LEAB
C
C
2A1
1A1
D
1B1
2 B1
D
C
C
D
D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2618 drw 01
2618 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
5.12
SEPTEMBER 1996
DSC-2618/7
1
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1OEAB
1
56
1OEBA
1OEAB
1
56
1OEBA
1LEAB
2
55
1LEBA
1LEAB
2
55
1LEBA
1CEAB
3
54
1CEBA
1CEAB
3
54
1CEBA
GND
4
53
GND
GND
4
53
GND
1A1
5
52
1B1
1 A1
5
52
1B1
1A2
6
51
1B2
1 A2
6
51
1B2
VCC
7
50
VCC
VCC
7
50
VCC
1A3
8
49
1B3
1 A3
8
49
1B3
1A4
9
48
1B4
1 A4
9
48
1B4
1A5
10
47
1B5
1 A5
10
47
1B5
GND
11
46
GND
GND
11
46
GND
1A6
12
45
1B6
1 A6
12
45
1B6
1A7
13
44
1B7
1 A7
13
44
1B7
1A8
14
1B8
1 A8
14
43
1B8
2A1
15
SO56-1 43
SO56-2
SO56-3 42
2B1
2 A1
15
42
2B1
2A2
16
41
2B2
2 A2
16
41
2B2
2A3
17
40
2B3
2 A3
17
40
2B3
GND
18
39
GND
GND
18
39
GND
2A4
19
38
2B4
2 A4
19
38
2B4
2A5
20
37
2B5
2 A5
20
37
2B5
2A6
21
36
2B6
2 A6
21
36
2B6
VCC
22
35
VCC
VCC
22
35
VCC
2A7
23
34
2B7
2 A7
23
34
2B7
2A8
24
33
2B8
2 A8
24
33
2B8
GND
25
32
GND
GND
25
32
GND
2CEAB
26
31
2CEBA
2CEAB
26
31
2CEBA
2LEAB
27
30
2LEBA
2LEAB
27
30
2LEBA
2OEAB
28
29
2OEBA
2OEAB
28
29
2OEBA
SSOP/
TSSOP/TVSOP
TOP VIEW
E56-1
2618 drw 04
2618 drw 03
CERPACK
TOP VIEW
5.12
2
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1, 2)
PIN DESCRIPTION
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xLEAB
For A-to-B (Symmetric with B-to-A)
Description
Latch
Status
Output
Buffers
xOEAB
xAx to xBx
xBx
A-to-B Output Enable Input (Active LOW)
Inputs
B-to-A Output Enable Input (Active LOW)
xCEAB xLEAB
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
xLEBA
B-to-A Latch Enable Input (Active LOW)
xAx
A-to-B Data Inputs or B-to-A 3-State Outputs
xBx
B-to-A Data Inputs or A-to-B 3-State Outputs
2618 tbl 01
H
X
X
Storing
High Z
X
H
X
Storing
X
L
L
L
Transparent
Current A Inputs
L
L
L
H
L
H
L
H
H
Storing
Transparent
Storing
Previous* A Inputs
High Z
High Z
NOTES:
2618 tbl 02
1. * Before xLEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using
xCEBA, x LEBA and xOEBA.
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
VTERM(3) Terminal Voltage with Respect to
–0.5 to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
Unit
V
I OUT
mA
DC Output Current
–60 to +120
Symbol
Parameter(1)
CIN
Input
Capacitance
CI/O
I/O
Capacitance
V
°C
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
Max. Unit
6.0
pF
8.0
NOTE:
1. This parameter is measured at characterization but not tested.
pF
2618 lnk 04
NOTES:
2618 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.12
3
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current (Input pins)(5)
Symbol
VIH
Min.
2.0
Typ.(2)
—
Max.
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
—
—
±1
—
—
±1
—
—
±1
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
II L
Input LOW Current (Input
pins)(5)
VI = GND
Input LOW Current (I/O pins)(5)
I OZH
High Impedance Output Current
VCC = Max.
VO = 2.7V
pins) (5)
I OZL
(3-State Output
VIK
Clamp Diode Voltage
I OS
Short Circuit Current
VH
Input Hysteresis
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = 0.5V
VCC = Min., IIN = –18mA
VCC = Max., VO =
GND (3)
—
VCC = Max., VIN = GND or VCC
—
Unit
V
µA
—
—
±1
—
–0.7
–1.2
V
–80
–140
–225
mA
—
100
—
mV
—
5
500
µA
2618 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16543T
Symbol
IO
Parameter
Output Drive Current
VOH
Output HIGH Voltage
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min.
–50
Typ.(2)
—
Max.
–180
Unit
mA
VCC = Min.
2.5
3.5
—
V
2.4
3.5
—
V
2.0
3.0
—
V
—
0.2
0.55
V
—
—
±1
I OH = –3mA
VIN = VIH or V IL
VOL
Output LOW Voltage
I OFF
Input/Output Power Off Leakage(5)
VCC = Min.
VIN = VIH or V IL
VCC = 0V, VIN or V O
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OH = –24mA MIL.
I OH = –32mA COM'L.(4)
I OL = 48mA MIL.
I OL = 64mA COM'L.
≤ 4.5V
µA
2618 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162543T
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
60
Typ.(2)
115
Max.
200
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–60
–115
–200
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or V IL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.55
V
I OH = –16mA MIL.
I OH = –24mA COM'L.
I OL = 16mA MIL.
I OL = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.12
2618 lnk 07
4
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
—
0.5
1.5
mA
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4)
VCC = Max., Outputs Open
xCEAB and xOEAB = GND
xCEBA = VCC
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open
fi = 10MHz
50% Duty Cycle
xLEAB, xCEAB and
xOEAB= GND
xCEBA = VCC
One Bit Toggling
VIN = VCC
VIN = GND
—
0.6
1.5
mA
VIN = 3.4V
VIN = GND
—
0.9
2.3
VCC = Max., Outputs Open
fi = 2.5MHz
50% Duty Cycle
xLEAB, xCEAB and
xOEAB= GND
xCEBA = VCC
Sixteen Bits Toggling
VIN = VCC
VIN = GND
—
2.4
4.5(5)
VIN = 3.4V
VIN = GND
—
6.4
16.5(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.12
2618 tbl 08
5
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16543T/162543T
Com'l.
Symbol
Parameter
tPLH
tPHL
Propagation Delay
Transparent Mode
xAx to xBx or xBx to xAx
tPLH Propagation Delay
tPHL xLEBA to xAx, xLEAB to xBx
tPZH Output Enable Time
tPZL xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tPHZ Output Disable Time
tPLZ xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tSU Set-up Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
tH
Hold Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
tW
xLEBA or xLEAB Pulse Width
LOW
tSK(o) Output Skew (3)
FCT16543AT/162543AT
Mil.
Com'l.
Mil.
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
CL = 50pF
RL = 500Ω
1.5
8.5
1.5
10.0
1.5
6.5
1.5
7.5
ns
1.5
12.5
1.5
14.0
1.5
8.0
1.5
9.0
ns
1.5
12.0
1.5
14.0
1.5
9.0
1.5
10.0
ns
1.5
9.0
1.5
13.0
1.5
7.5
1.5
8.5
ns
3.0
—
3.0
—
2.0
—
2.0
—
ns
2.0
—
2.0
—
2.0
—
2.0
—
ns
5.0
—
5.0
—
5.0
—
5.0
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
ns
2618 tbl 09
FCT16543CT/162543CT
Com'l.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Transparent Mode
xAx to xBx or xBx to xAx
tPLH Propagation Delay
tPHL xLEBA to xAx, xLEAB to xBx
tPZH Output Enable Time
tPZL xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tPHZ Output Disable Time
tPLZ xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tSU Set-up Time, HIGH or LOW
xAx or xBx to xLEBA or xLEAB
tH
Hold Time HIGH or LOW
xAx or xBx to xLEBA or xLEAB
tW
xLEBA or xLEAB Pulse Width
LOW
tSK(o) Output Skew (3)
Condition(1)
Min.(2)
CL = 50pF
RL = 500Ω
1.5
FCT16543ET/162543ET
Mil.
Max.
Min.(2)
5.3
1.5
1.5
7.0
1.5
Com'l.
Max.
Min.(2)
6.1
1.5
1.5
8.0
8.0
1.5
1.5
6.5
2.0
Mil.
Max.
Min.(2)
Max.
Unit
3.4
—
—
ns
1.5
3.7
—
—
ns
9.0
1.5
4.8
—
—
ns
1.5
7.5
1.5
4.0
—
—
ns
—
2.0
—
1.0
—
—
—
ns
2.0
—
2.0
—
1.0
—
—
—
ns
5.0
—
5.0
—
3.0 (4)
—
—
—
ns
—
0.5
—
0.5
—
0.5
—
—
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5.12
2618 tbl 10
6
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
D.U.T.
Open
All Other Tests
50pF
RT
500Ω
DEFINITIONS:
2618 lnk 10
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
CL
2618 drw 05
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
2618 drw 07
2618 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
1.5V
0V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
2618 drw 08
SWITCH
OPEN
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2618 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.12
7
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
X
FCT XXXX
Device
Temperature
Type
Range
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
16543T
16-Bit Latched Transceiver
16543AT
16543CT
16543ET
162543T
162543AT
162543CT
162543ET
54
74
5.12
–55°C to +125°C
–40°C to +85°C
2618 drw 10
8
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