IDT IDT54FCT162646ETPFB Fast cmos 16-bit bus transceiver/ registers (3-state) Datasheet

Integrated Device Technology, Inc.
FAST CMOS 16-BIT BUS IDT54/74FCT16646T/AT/CT/ET
IDT54/74FCT162646T/AT/CT/ET
TRANSCEIVER/
REGISTERS (3-STATE)
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16646T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162646T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
DESCRIPTION:
The IDT54/74FCT16646T/AT/CT/ET and IDT54/
74FCT162646T/AT/CT/ET 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power devices are organized as two independent 8-bit bus transceivers with 3-state D-type registers.
The control circuitry is organized for multiplexed transmission
of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register features direction control (xDIR), over-riding Output Enable control (xOE) and Select lines (xSAB and xSBA) to select either
real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data
bus, or both, can be stored in the internal registers by the
LOW-to-HIGH transitions at the appropriate clock pins. Flowthrough organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The IDT54/74FCT16646T/AT/CT/ET are ideally suited for
driving high-capacitance loads and low-impedance
backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used
as backplane drivers.
The IDT54/74FCT162646T/AT/CT/ET have balanced
output drive with current limiting resistors. This offers low
ground bounce, minimal undershoot, and controlled output
fall times–reducing the need for external series terminating
resistors. The IDT54/74FCT162646T/AT/CT/ET are plug-in
replacements for the IDT54/74FCT16646T/AT/CT/ET and
54/74ABT16646 for on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OE
2OE
1DIR
2DIR
1CLKBA
2CLKBA
1SBA
2SBA
1CLKAB
2CLKAB
1SAB
1A1
2SAB
B REG
B REG
D
D
C
C
1B1
A REG
2A1
D
C
C
TO 7 OTHER CHANNELS
2B1
A REG
D
TO 7 OTHER CHANNELS
2540 drw 01
2540 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
5.13
AUGUST 1996
DSC-4231/9
1
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1DIR
1
56
1OE
1CLKAB
2
55
1CLKBA
1SBA
1SAB
3
54
1SBA
53
GND
GND
4
53
GND
5
52
1B1
1A1
5
52
1B1
1A 2
6
51
1B2
1A2
6
51
1B2
VCC
7
50
VCC
VCC
7
50
VCC
1A 3
8
49
1B3
1A3
8
49
1B3
1A 4
9
48
1B4
1A4
9
48
1B4
1A5
10
47
1B5
1A5
10
47
1B5
GND
11
46
GND
GND
11
46
GND
1A 6
12
45
1B6
1A6
12
45
1B6
1A 7
13
44
1B7
1A7
13
44
1B7
1A 8
14
1B8
1A8
14
43
1B8
2A1
15
SO56-1 43
SO56-2
SO56-3 42
2B1
2A1
15
42
2B1
2A 2
16
41
2B2
2A2
16
41
2B2
2A 3
17
40
2B3
2A3
17
40
2B3
GND
18
39
GND
GND
18
39
GND
2A 4
19
38
2B4
2A4
19
38
2B4
2A5
20
37
2B5
2A5
20
37
2B5
2A6
21
36
2B6
2A6
21
36
2B6
VCC
22
35
VCC
VCC
22
35
VCC
2A 7
23
34
2B7
2A7
23
34
2B7
2A8
24
33
2B8
2A8
24
33
2B8
GND
25
32
GND
GND
25
32
GND
2SAB
26
31
2SBA
2SAB
26
31
2SBA
2CLKAB
27
30
2CLKBA
2CLKAB
27
30
2CLKBA
2DIR
28
29
2OE
2DIR
28
29
2OE
1DIR
1
56
1OE
1CLKAB
2
55
1CLKBA
1SAB
3
54
GND
4
1A1
SSOP/
TSSOP/TVSOP
TOP VIEW
E56-1
2540 drw 03
CERPACK
TOP VIEW
5.13
2540 drw 04
2
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input
Capacitance
CI/O
I/O
Capacitance
Pin Names
xAx
Description
Data Register A Inputs
Data Register B Outputs
xBx
Data Register B Inputs
Data Register A Outputs
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA
xDIR, xOE
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
Max. Unit
6.0
pF
8.0
NOTE:
1. This parameter is measured at characterization but not tested.
Output Data Source Select Inputs
pF
2540 tbl 02
Output Enable Inputs
2540 tbl 01
FUNCTION TABLE(2)
Data I/O(1)
Inputs
xOE
xDIR
H
H
X
X
H or L
↑
L
L
L
L
L
L
H
H
X
X
X
H or L
xCLKAB xCLKBA
Operation or Function
xSAB
xSBA
xAx
xBx
H or L
↑
X
X
X
X
Input
Input
Isolation
Store A and B Data
X
H or L
X
X
X
X
L
H
L
H
X
X
Output
Input
Input
Output
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data
input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
2540 tbl 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
VTERM(3) Terminal Voltage with Respect to
–0.5 to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
Unit
V
I OUT
mA
DC Output Current
–60 to +120
V
°C
2540 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.13
3
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
BUS
A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
B
2540 drw 06
2540 drw 05
xDIR
L
xOE
xCLKAB
xCLKBA
xSAB
xSBA
xDIR
L
X
X
X
L
H
xOE
L
xCLKBA
xSAB
xSBA
X
X
L
X
REAL-TIME TRANSFER
BUS A TO B
REAL-TIME TRANSFER
BUS B TO A
BUS
A
xCLKAB
BUS
A
BUS
B
BUS
B
2540 drw 08
2540 drw 07
xDIR
xOE
xCLKAB
xCLKBA
xSAB
H
L
X
X
L
L
↑
X
↑
X
X
X
X
H
↑
↑
X
X
xDIR
xSBA
STORAGE FROM
A AND/OR B
(1)
xOE
xCLKAB
xCLKBA
xSAB
xSBA
L
L
X
H or L
X
H
H
L
H or L
X
H
X
TRANSFER STORED
DATA TO A AND/OR B
NOTE:
1. Cannot transfer data to A bus and B bus simultaneously.
5.13
4
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current (Input pins)(5)
Symbol
VIH
Min.
2.0
Typ.(2)
—
Max.
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
—
—
±1
VI = GND
—
—
±1
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
II L
Input LOW Current (Input
Input LOW Current (I/O
I OZH
pins)(5)
pins)(5)
High Impedance Output Current
VCC = Max.
pins) (5)
—
Unit
V
µA
I OZL
(3-State Output
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
I OS
Short Circuit Current
VCC = Max., VO = GND (3)
–80
–140
–225
mA
VH
Input Hysteresis
—
100
—
mV
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
—
5
500
µA
—
VCC = Max., VIN = GND or VCC
2540 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16646T
Symbol
IO
Parameter
Output Drive Current
VOH
Output HIGH Voltage
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min.
–50
Typ.(2)
—
Max.
–180
Unit
mA
VCC = Min.
2.5
3.5
—
V
2.4
3.5
—
V
2.0
3.0
—
V
—
0.2
0.55
V
—
—
±1
I OH = –3mA
VIN = VIH or V IL
VOL
Output LOW Voltage
I OFF
Input/Output Power Off Leakage(5)
VCC = Min.
VIN = VIH or V IL
VCC = 0V, VIN or V O
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OH = –24mA MIL.
I OH = –32mA COM'L.(4)
I OL = 48mA MIL.
I OL = 64mA COM'L.
≤ 4.5V
µA
2540 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162646T
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
60
Typ.(2)
115
Max.
200
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–60
–115
–200
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or V IL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.55
V
I OH = –16mA MIL.
I OH = –24mA COM'L.
I OL = 16mA MIL.
I OL = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.13
2540 lnk 07
5
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
—
0.5
1.5
mA
VIN = VCC
VIN = GND
—
75
120
µA/
MHz
VCC = Max.
Outputs Open
fCP = 10MHz (xCLKBA)
50% Duty Cycle
xDIR = xOE = GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VIN = VCC
VIN = GND
—
0.8
1.7
mA
VIN = 3.4V
VIN = GND
—
1.3
3.2
VCC = Max.
Outputs Open
fCP = 10MHz (xCLKBA)
50% Duty Cycle
xDIR = xOE = GND
Sixteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
VIN = VCC
VIN = GND
—
3.8
6.5 (5)
VIN = 3.4V
VIN = GND
—
8.3
20.0 (5)
Symbol
Parameter
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current (4)
VCC = Max.
Outputs Open
xDIR = xOE= GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current (6)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.13
2540 tbl 08
6
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16646T/162646T
Com'l.
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
tSK(o)
Parameter
Propagation Delay
Bus to Bus
Output Enable Time
xDIR or xOE to Bus
Output Disable Time
xDIR or xOE to Bus
Propagation Delay
Clock to Bus
Propagation Delay
xSBA or xSAB to Bus
Set-up Time HIGH or
LOW Bus to Clock
Hold Time HIGH or
LOW Bus to Clock
Clock Pulse Width
HIGH or LOW
Output Skew (3)
Condition(1)
Min.(2)
CL = 50pF
RL = 500Ω
2.0
FCT16646AT/162646AT
Mil.
Max.
Min.(2)
9.0
2.0
2.0
14.0
2.0
Com'l.
Max.
Min.(2)
11.0
2.0
2.0
15.0
9.0
2.0
2.0
9.0
2.0
Mil.
Max.
Min.(2)
Max.
Unit
6.3
2.0
7.7
ns
2.0
9.8
2.0
10.5
ns
11.0
2.0
6.3
2.0
7.7
ns
2.0
10.0
2.0
6.3
2.0
7.0
ns
11.0
2.0
12.0
2.0
7.7
2.0
8.4
ns
4.0
—
4.5
—
2.0
—
2.0
—
ns
2.0
—
2.0
—
1.5
—
1.5
—
ns
6.0
—
6.0
—
5.0
—
5.0
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
ns
2540 tbl 09
FCT16646CT/162646CT
Com'l.
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
tSK(o)
Parameter
Propagation Delay
Bus to Bus
Output Enable Time
xDIR or xOE to Bus
Output Disable Time
xDIR or xOE to Bus
Propagation Delay
Clock to Bus
Propagation Delay
xSBA or xSAB to Bus
Set-up Time HIGH or
LOW Bus to Clock
Hold Time HIGH or
LOW Bus to Clock
Clock Pulse Width
HIGH or LOW
Output Skew (3)
Condition(1)
Min.(2)
CL = 50pF
RL = 500Ω
1.5
FCT16646ET/162646ET
Mil.
Max.
Min.(2)
5.4
1.5
1.5
7.8
1.5
Com'l.
Max.
Min.(2)
6.0
1.5
1.5
8.9
6.3
1.5
1.5
5.7
1.5
Mil.
Max.
Min.(2)
Max.
Unit
3.8
—
—
ns
1.5
4.8
—
—
ns
7.7
1.5
4.0
—
—
ns
1.5
6.3
1.5
3.8
—
—
ns
6.2
1.5
7.0
1.5
4.2
—
—
ns
2.0
—
2.0
—
2.0
—
—
—
ns
1.5
—
1.5
—
0.0
—
—
—
ns
5.0
—
5.0
—
3.0 (4)
—
—
—
ns
—
0.5
—
0.5
—
0.5
—
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5.13
2540 tbl10
7
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
500Ω
VIN
Open Drain
Disable Low
Closed
Open
All Other Tests
D.U.T.
50pF
RT
Switch
Enable Low
V OUT
Pulse
Generator
Test
2556 lnk 10
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2556 drw 05
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2556 drw 07
3V
1.5V
0V
tH
2556 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
CONTROL
INPUT
tPZL
VOH
1.5V
VOL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
2556 drw 08
SWITCH
OPEN
0V
tPLZ
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2556 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.13
8
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
Temperature
Range
FCT
XXXX
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
16646T
Non-Inverting 16-Bit Transceiver/Register
16646AT
16646CT
16646ET
162646T
162646AT
162646CT
162646ET
54
74
–55°C to +125°C
–40°C to +85°C
2540 drw 14
5.13
9
Similar pages