IDT IDT54FCT16501CTE Fast cmos 18-bit registered transceiver Datasheet

IDT54/74FCT16501AT/CT/ET
IDT54/74FCT162501AT/CT/ET
IDT54/74FCT162H501AT/CT/ET
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
Integrated Device Technology, Inc.
CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type
• Common features:
flip-flops to allow data flow in transparent, latched and clocked
– 0.5 MICRON CMOS Technology
modes. Data flow in each direction is controlled by output– High-speed, low-power CMOS replacement for
enable (OEAB and OEBA), latch enable (LEAB and LEBA)
ABT functions
and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow,
– Typical tSK(o) (Output Skew) < 250ps
the
device
operates in transparent mode when LEAB is HIGH.
– Low input and output leakage ≤ 1µA (max.)
When
LEAB
is LOW, the A data is latched if CLKAB is held at
– ESD > 2000V per MIL-STD-883, Method 3015;
a
HIGH
or
LOW
logic level. If LEAB is LOW, the A bus data
> 200V using machine model (C = 200pF, R = 0)
is
stored
in
the
latch/flip-flop
on the LOW-to-HIGH transition of
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
CLKAB.
OEAB
is
the
output
enable for the B port. Data flow
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
from
the
B
port
to
the
A
port
is
similar
but requires using OEBA,
– Extended commercial range of -40°C to +85°C
LEBA
and
CLKBA.
Flow-through
organization
of signal pins
• Features for FCT16501AT/CT/ET:
simplifies
layout.
All
inputs
are
designed
with
hysteresis
for
– High drive outputs (-32mA IOH, 64mA IOL)
improved
noise
margin.
– Power off disable outputs permit “live insertion”
The FCT16501AT/CT/ET are ideally suited for driving
– Typical VOLP (Output Ground Bounce) < 1.0V at
high-capacitance
loads and low-impedance backplanes. The
VCC = 5V, TA = 25°C
output
buffers
are
designed with power off disable capability
• Features for FCT162501AT/CT/ET:
to
allow
"live
insertion"
of boards when used as backplane
– Balanced Output Drivers: ±24mA (commercial),
drivers.
±16mA (military)
The FCT162501AT/CT/ET have balanced output drive
– Reduced system switching noise
with
current limiting resistors. This offers low ground bounce,
– Typical VOLP (Output Ground Bounce) < 0.6V at
minimal
undershoot, and controlled output fall times–reducing
VCC = 5V,TA = 25°C
the
need
for external series terminating resistors. The
• Features for FCT162H501AT/CT/ET:
FCT162501AT/CT/ET
are plug-in replacements for the
– Bus Hold retains last active bus state during 3-state
FCT16501AT/CT/ET
and
ABT16501 for on-board bus inter– Eliminates the need for external pull up resistors
face applications.
The FCT162H501AT/CT/ET have "Bus Hold" which reDESCRIPTION:
tains the input's last state whenever the input goes to high
The FCT16501AT/CT/ET and FCT162501AT/CT/ET 18- impedance. This prevents "floating" inputs and eliminates the
bit registered transceivers are built using advanced dual metal need for pull-up/down resistors.
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
C
C
D
D
B1
C
C
D
D
TO 17 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
5.10
2547 drw 01
AUGUST 1996
DSC-2547/8
1
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB
1
56
GND
OEAB
1
56
GND
LEAB
2
55
CLKAB
LEAB
2
55
CLKAB
A1
3
54
B1
A1
3
54
B1
GND
4
53
GND
GND
4
53
GND
A2
5
52
B2
A2
5
52
B2
A3
6
51
B3
A3
6
51
B3
VCC
7
50
VCC
VCC
7
50
VCC
A4
8
49
B4
A4
8
49
B4
A5
9
48
B5
A5
9
48
B5
A6
10
47
B6
A6
10
47
B6
GND
11
46
GND
GND
11
46
GND
A7
12
45
B7
A7
12
45
B7
A8
13
44
B8
A8
13
44
B8
A9
14
B9
A9
14
43
B9
A10
15
SO56-1 43
SO56-2
SO56-3 42
B10
A10
15
42
B10
A11
16
41
B11
A11
16
41
B11
A12
17
40
B12
A12
17
40
B12
GND
18
39
GND
GND
18
39
GND
A13
19
38
B13
A13
19
38
B13
A14
20
37
B14
A14
20
37
B14
A15
21
36
B15
A15
21
36
B15
VCC
22
35
VCC
VCC
22
35
VCC
A16
23
34
B16
A16
23
34
B16
A17
24
33
B17
A17
24
33
B17
GND
25
32
GND
GND
25
32
GND
A18
26
31
B18
A18
26
31
B18
OEBA
27
30
CLKBA
OEBA
27
30
CLKBA
LEBA
28
29
GND
LEBA
28
29
GND
SSOP/
TSSOP/TVSOP
TOP VIEW
E56-1
2547 drw 03
2547 drw 02
CERPACK
TOP VIEW
5.10
2
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1,4)
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
L
X
X
X
Z
LEBA
B-to-A Latch Enable Input
H
H
X
L
L
CLKAB
A-to-B Clock Input
H
H
X
H
H
B-to-A Clock Input
H
L
↑
L
L
(1)
H
L
↑
H
H
(1)
H
L
L
X
B(2)
H
L
H
X
B(3)
CLKBA
Ax
Bx
OEAB
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTE:
2547 tbl 01
1. On FCT16xH501T these pins have “Bus Hold”. All other pins are standard
inputs, outputs or I/Os.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
VTERM(3) Terminal Voltage with Respect to
–0.5 to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
Unit
V
I OUT
mA
DC Output Current
–60 to +120
V
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
Inputs
LEAB
CLKAB
Outputs
Bx
Ax
NOTES:
2547 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
CAPACITANCE (TA = +25°C, f = 1.0MHz)
2547 lnk 03
Symbol
Parameter(1)
CIN
Input
Capacitance
CI/O
I/O
Capacitance
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
Max. Unit
6.0
pF
8.0
NOTE:
1. This parameter is measured at characterization but not tested.
5.10
pF
2547 lnk 04
3
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (STANDARD PARTS)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current (Input pins)(5)
Symbol
VIH
Min.
2.0
Typ.(2)
—
Max.
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
—
—
±1
—
—
±1
—
—
±1
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
II L
Input LOW Current (Input
pins)(5)
VI = GND
Input LOW Current (I/O pins)(5)
I OZH
High Impedance Output Current
VCC = Max.
VO = 2.7V
pins) (5)
I OZL
(3-State Output
VIK
Clamp Diode Voltage
I OS
Short Circuit Current
VH
Input Hysteresis
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = 0.5V
VCC = Min., IIN = –18mA
VCC = Max., VO =
GND (3)
—
VCC = Max., VIN = GND or VCC
—
Unit
V
µA
—
—
±1
—
–0.7
–1.2
V
–80
–140
–225
mA
—
100
—
mV
—
5
500
µA
2547 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16501T
Symbol
IO
Parameter
Output Drive Current
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min.
–50
Typ.(2)
—
Max.
–180
Unit
mA
VOH
Output HIGH Voltage
VCC = Min.
2.5
3.5
—
V
2.4
3.5
—
V
2.0
3.0
—
V
—
0.2
0.55
V
—
—
±1
I OH = –3mA
VIN = VIH or V IL
VOL
Output LOW Voltage
I OFF
Input/Output Power Off Leakage(5)
VCC = Min.
VIN = VIH or V IL
VCC = 0V, VIN or V O
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OH = –24mA MIL.
I OH = –32mA COM'L.(4)
I OL = 48mA MIL.
I OL = 64mA COM'L.
≤ 4.5V
µA
2547 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162501T
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
60
Typ.(2)
115
Max.
200
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–60
–115
–200
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or V IL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.55
V
I OH = –16mA MIL.
I OH = –24mA COM'L.
I OL = 16mA MIL.
I OL = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.10
2547 lnk 07
4
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10%
Symbol
VIH
VIL
II H
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
Standard
Input(5)
HIGH
Standard
I/O(5)
—
—
±1
Current(4)
Bus-Hold Input
—
—
±100
Bus-Hold I/O
—
—
±100
Input
VI = VCC
Input
Standard
—
—
±1
LOW
Standard I/O(5)
—
—
±1
Current(4)
Bus-Hold Input
—
—
±100
I BHH
Bus Hold
Bus-Hold Input
I BHL
Sustain
Current(4)
High Impedance Output Current
II L
Input(5)
VI = GND
—
—
±100
VI = 2.0V
–50
—
—
VI = 0.8V
+50
—
—
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
Bus-Hold I/O
I OZH
VCC = Min.
VCC = Max.
pins) (5,6)
µA
µA
I OZL
(3-State Output
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
I OS
Short Circuit Current
VCC = Max., VO = GND(3)
–80
–140
–225
mA
VH
Input Hysteresis
—
100
—
mV
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
—
5
500
µA
—
VCC = Max., VIN = GND or VCC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
6. Does not include Bus Hold I/O pins.
5.10
2547 lnk 08
5
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
ICCD
Dynamic Power Supply Current(4)
VCC = Max., Outputs Open
VIN = VCC
OEAB = OEBA = VCC or GND VIN = GND
One Input Toggling
50% Duty Cycle
—
75
120
µA/
MHz
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VIN = VCC
VIN = GND
—
0.8
1.7
mA
VIN = 3.4V
VIN = GND
—
1.3
3.2
VCC = Max., Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
Eighteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
VIN = VCC
VIN = GND
—
3.8
6.5(5)
VIN = 3.4V
VIN = GND
—
8.5
20.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.10
2547 tbl 09
6
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16501AT/162501AT
Com'l.
Mil.
Com'l.
Mil.
FCT16501ET/162501ET
Com'l.
Mil.
Symbol
Parameter
Condition(1)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
fMAX
CLKAB or CLKBA frequency(4)
CL = 50pF
—
150
—
150
—
150
—
150
—
150
—
—
MHz
Propagation Delay
Ax to Bx or Bx to Ax
Propagation Delay
LEBA to Ax, LEAB to Bx
Propagation Delay
CLKBA to Ax, CLKAB to Bx
Output Enable Time
OEBA to Ax, OEAB to Bx
Output Disable Time
OEBA to Ax, OEAB to Bx
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tH
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tSU Set-up Time
Clock
HIGH or LOW
LOW
Ax to LEAB,
Clock
Bx to LEBA
HIGH
tH
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
tW
LEAB or LEBA Pulse Width
HIGH(4)
tW
CLKAB or CLKBA Pulse Width
HIGH or LOW(4)
tSK(o) Output Skew (3)
RL = 500Ω
1.5
5.1
1.5
5.6
1.5
4.6
1.5
4.6
1.5
3.8
—
—
ns
1.5
5.6
1.5
6.0
1.5
5.3
1.5
5.6
1.5
4.2
—
—
ns
1.5
5.6
1.5
6.0
1.5
5.3
1.5
5.4
1.5
4.2
—
—
ns
1.5
6.0
1.5
6.4
1.5
5.6
1.5
6.0
1.5
4.8
—
—
ns
1.5
5.6
1.5
6.0
1.5
5.2
1.5
5.6
1.5
5.2
—
—
ns
3.0
—
3.0
—
3.0
—
3.0
—
2.4
—
—
—
ns
0
—
0
—
0
—
0
—
0
—
—
—
ns
3.0
—
3.0
—
3.0
—
3.0
—
2.0
—
—
—
ns
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
—
—
ns
1.5
—
1.5
—
1.5
—
1.5
—
0.5
—
—
—
ns
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
—
—
ns
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
—
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
—
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Min.(2)
FCT16501CT/162501CT
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5.10
Max. Unit
2547 tbl 10
7
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
500Ω
Switch
Open Drain
Disable Low
Closed
Enable Low
V OUT
VIN
Pulse
Generator
Test
7.0V
Open
All Other Tests
D.U.T.
50pF
RT
2547 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2547 drw 04
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2547 drw 06
3V
1.5V
0V
tH
2547 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
0V
CONTROL
INPUT
tPZL
VOH
1.5V
VOL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
tPZH
OUTPUT
NORMALLY
HIGH
2547 drw 07
SWITCH
OPEN
3.5V
3.5V
1.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
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NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
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8
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT X
FCT
X
Temperature
Drive
Range
X
XXXX
X
Bus Hold Device Type Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
501AT
501CT
501ET
Non-Inverting 18-Bit Registered Transceiver
Blank
H
Standard
Bus Hold
16
162
16-Bit High Drive
16-Bit Balanced Drive
54
74
–55°C to +125°C
–40°C to +85°C
2547 drw 09
5.10
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