IDT IDT54FCT16841CTPFB Fast cmos 20-bit transparent latch Datasheet

FAST CMOS 20-BIT
TRANSPARENT
LATCHES
IDT54/74FCT16841AT/BT/CT/ET
IDT54/74FCT162841AT/BT/CT/ET
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16841AT/BT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162841AT/BT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
The FCT16841AT/BT/CT/ET and FCT162841AT/BT/CT/
ET 20-bit transparent D-type latches are built using advanced
dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be
used for implementing memory address latches, I/O ports,
and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 10-bit latches or
one 20-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16841AT/BT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162841AT/BT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162841AT/BT/CT/ET are plug-in replacements for the
FCT16841AT/BT/CT/ET and ABT16841 for on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OE
2OE
1LE
2LE
1D1
2D1
D
D
1Q1
2Q1
C
C
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
2556 drw 02
2556 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
5.18
JULY 1996
DSC-2556/7
1
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1OE
1
56
1LE
1OE
1
56
1LE
1Q1
2
55
1D1
1Q1
2
55
1D 1
1Q2
3
54
1D2
1Q2
3
54
1D 2
GND
4
53
GND
GND
4
53
GND
1Q3
5
52
1D3
1Q3
5
52
1D 3
1Q4
6
51
1D4
1Q4
6
51
1D 4
VCC
7
50
VCC
VCC
7
50
VCC
1Q5
8
49
1D5
1Q5
8
49
1D 5
1Q6
9
48
1D6
1Q6
9
48
1D 6
1Q7
10
47
1D7
1Q7
10
47
1D 7
GND
11
46
GND
GND
11
46
GND
1Q8
12
45
1D8
1Q8
12
45
1D 8
1Q9
13
44
1D9
1Q9
13
44
1D 9
43
1D10
1Q10
1D10
1Q 10
14
2Q1
14 SO56-1 43
SO56-2
15 SO56-3 42
2D1
2Q1
15
42
2D 1
2Q2
16
41
2D2
2Q2
16
41
2D 2
2Q3
17
40
2D3
2Q3
17
40
2D 3
GND
18
39
GND
GND
18
39
GND
2Q4
19
38
2D4
2Q4
19
38
2D 4
2Q5
20
37
2D5
2Q5
20
37
2D 5
2Q6
21
36
2D6
2Q6
21
36
2D 6
VCC
22
35
VCC
VCC
22
35
VCC
2Q7
23
34
2D7
2Q7
23
34
2D 7
2Q8
24
33
2D8
2Q8
24
33
2D 8
GND
25
32
GND
GND
25
32
GND
2Q9
26
31
2D9
2Q9
26
31
2D 9
2Q10
27
30
2D10
2Q 10
27
30
2D10
2OE
28
29
2LE
2OE
28
29
2LE
E56-1
2556 drw 03
2556 drw 04
SSOP/
TSSOP/TVSOP
TOP VIEW
CERPACK
TOP VIEW
5.18
2
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
xDx
Description
xDx
Inputs
xLE
xOE
Outputs
xQx
xLE
Latch Enable Input (Active HIGH)
H
H
L
H
xOE
Output Enable Input (Active LOW)
L
H
L
L
xQx
3-State Outputs
X
L
L
Q(2)
X
X
H
Z
Data Inputs
2556 tbl 01
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2. Output level before xLE HIGH-to-LOW Transition.
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
VTERM(3) Terminal Voltage with Respect to
–0.5 to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
Unit
V
I OUT
mA
DC Output Current
–60 to +120
2556 tbl 02
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
V
°C
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
Max. Unit
6.0
pF
8.0
pF
2556 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
2556 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.18
3
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current (Input pins)(5)
Symbol
VIH
Min.
2.0
Typ.(2)
—
Max.
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
—
—
±1
—
—
±1
—
—
±1
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
II L
Input LOW Current (Input
pins)(5)
VI = GND
Input LOW Current (I/O pins)(5)
I OZH
High Impedance Output Current
VCC = Max.
VO = 2.7V
pins) (5)
I OZL
(3-State Output
VIK
Clamp Diode Voltage
I OS
Short Circuit Current
VH
Input Hysteresis
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = 0.5V
VCC = Min., IIN = –18mA
VCC = Max., VO =
GND (3)
—
VCC = Max., VIN = GND or VCC
—
Unit
V
µA
—
—
±1
—
–0.7
–1.2
V
–80
–140
–225
mA
—
100
—
mV
—
5
500
µA
2556 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16841T
Symbol
IO
Parameter
Output Drive Current
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min.
–50
Typ.(2)
—
Max.
–180
Unit
mA
VOH
Output HIGH Voltage
VCC = Min.
2.5
3.5
—
V
2.4
3.5
—
V
2.0
3.0
—
V
—
0.2
0.55
V
—
—
±1
I OH = –3mA
VIN = VIH or V IL
VOL
Output LOW Voltage
I OFF
Input/Output Power Off Leakage(5)
VCC = Min.
VIN = VIH or V IL
VCC = 0V, VIN or V O
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OH = –24mA MIL.
I OH = –32mA COM'L.(4)
I OL = 48mA MIL.
I OL = 64mA COM'L.
≤ 4.5V
µA
2556 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162841T
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
60
Typ.(2)
115
Max.
200
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–60
–115
–200
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or V IL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.55
V
I OH = –16mA MIL.
I OH = –24mA COM'L.
I OL = 16mA MIL.
I OL = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.18
2556 lnk 07
4
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
IC
Total Power Supply Current (6)
VCC = Max.
Outputs Open
fi =10MHz
50% Duty Cycle
xOE = GND
xLE = VCC
One Bit Toggling
VIN = VCC
VIN = GND
—
0.6
1.5
mA
VIN = 3.4V
VIN = GND
—
0.9
2.3
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE = GND
xLE = VCC
Twenty Bits Toggling
VIN = VCC
VIN = GND
—
3.0
5.5 (5)
VIN = 3.4V
VIN = GND
—
8.0
20.5 (5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.18
2556 tbl 08
5
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16841AT/162841AT
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Propagation Delay
xDx to xQx
(LE = HIGH)
Propagation Delay
xLE to xQx
Output Enable Time
xOE to xQx
Output Disable Time
xOE to xQx
tW
Set-Up Time HIGH or LOW,
xDx to xLE
Hold Time HIGH or LOW,
xDx to xLE
xLE Pulse Width HIGH
tSK(o)
Output skew(3)
tH
FCT16841BT/162841BT
Mil.
Com'l.
Mil.
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 5pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
1.5
9.0
1.5
10.0
1.5
6.5
1.5
7.5
ns
1.5
13.0
1.5
15.0
1.5
13.0
1.5
15.0
1.5
12.0
1.5
13.0
1.5
8.0
1.5
10.5
1.5
16.0
1.5
20.0
1.5
15.5
1.5
18.0
1.5
11.5
1.5
13.0
1.5
8.0
1.5
8.5
1.5
23.0
1.5
25.0
1.5
14.0
1.5
15.0
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
1.5
8.0
1.5
10.0
1.5
7.0
1.5
7.5
2.5
—
2.5
—
2.5
—
2.5
—
ns
2.5
—
3.0
—
2.5
—
2.5
—
ns
4.0 (4)
—
5.0
—
4.0 (4)
—
4.0 (4)
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
5.18
ns
ns
ns
2556 tbl 09
6
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16841CT/162841CT
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Propagation Delay
xDx to xQx
(LE = HIGH)
Propagation Delay
xLE to xQx
Output Enable Time
xOE to xQx
Output Disable Time
xOE to xQx
tW
Set-Up Time HIGH or LOW,
xDx to xLE
Hold Time HIGH or LOW,
xDx to xLE
xLE Pulse Width HIGH
tSK(o)
Output skew(3)
tH
Condition(1)
Min.(2)
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 5pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
1.5
FCT16841ET/162841ET
Mil.
Max.
Min.(2)
5.5
1.5
1.5
13.0
1.5
Com'l.
Max.
Min.(2)
6.3
1.5
1.5
15.0
6.4
1.5
1.5
15.0
1.5
Mil.
Max.
Min.(2)
Max.
Unit
3.4
—
—
ns
1.5
7.5
—
—
6.8
1.5
3.7
—
—
1.5
16.0
1.5
7.5
—
—
6.5
1.5
7.3
1.5
4.4
—
—
1.5
12.0
1.5
13.0
1.5
9.0
—
—
1.5
5.7
1.5
6.0
1.5
3.6
—
—
1.5
6.0
1.5
6.3
1.5
3.6
—
—
2.5
—
2.5
—
1.0
—
—
—
ns
2.5
—
2.5
—
1.0
—
—
—
ns
4.0 (4)
—
4.0 (4)
—
3.0 (4)
—
—
—
ns
—
0.5
—
0.5
—
0.5
—
—
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
5.18
ns
ns
ns
ns
2556 tbl 10
7
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
500Ω
VIN
Open Drain
Disable Low
Closed
Open
All Other Tests
D.U.T.
50pF
RT
Switch
Enable Low
V OUT
Pulse
Generator
Test
2556 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2556 drw 05
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2556 drw 07
3V
1.5V
0V
tH
2556 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
CONTROL
INPUT
tPZL
VOH
1.5V
VOL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
2556 drw 08
SWITCH
OPEN
0V
tPLZ
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2556 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.18
8
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
Temp. Range
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
16841AT Non-Inverting 20-Bit Transparent Latch
16841BT
16841CT
16841ET
162841AT
162841BT
162841CT
162841ET
54
74
–55°C to +125°C
–40°C to +85°C
2556 drw 10
5.18
9
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