IDT IDT54FCT273APB Fast cmos octal flip-flop with master reset Datasheet


IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset ( ) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the
input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
•
•
•
•
•
•
•
•
•
IDT54/74FCT273 equivalent to FAST speed;
IDT54/74FCT273A 45% faster than FAST
IDT54/74FCT273C 55% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
IOL = 48mA (commercial) and 32mA (military)
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST
(5µA max.)
Octal D flip-flop with Master Reset
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
MR
MR
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
CP
D
Q
D
CP
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
CP
RD
RD
MR
O0
O1
O2
O3
O4
O5
O6
O7
2558 drw 01
1
20
2
19
3
4
5
6
7
18
P20-1
D20-1
SO20-2
&
E20-1
17
16
15
14
8
13
9
12
10
11
INDEX
Vcc
O7
D7
D6
O6
O5
D5
D4
O4
CP
3 2
D1
O1
O2
D2
D3
4
5
6
1
20 19
18
L20-2
17
16
7
15
8
14
9 10 11 12 13
O3
GND
CP
O4
D4
MR
O0
D0
D1
O1
O2
D2
D3
O3
GND
D0
O0
MR
Vcc
O7
PIN CONFIGURATIONS
DIP/SOIC/CERPACK
TOP VIEW
D7
D6
O6
O5
D5
2558 drw 02
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1992 Integrated Device Technology, Inc.
7.10
MAY 1992
DSC-4609/2
1
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
FUNCTION TABLE
Pin Names
Description
MR
DN
Data Input
Operating Mode
Master Reset (Active LOW)
Reset (Clear)
CP
Clock Pulse Input (Active Rising Edge)
Load “1”
ON
Data Outputs
Load “0”
H
MR
2558 tbl 05
VTERM(2)
Rating
Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
to GND
Outputs
ON
CP
DN
L
X
X
L
H
↑
h
H
↑
l
L
NOTES:
2558 tbl 06
H = HIGH voltage level steady-state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t care
↑ = LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Inputs
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
Military
Unit
–0.5 to +7.0
–0.5 to +7.0
V
–0.5 to VCC
–0.5 to VCC
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
IOUT
DC Output Current
120
120
mA
Symbol
Parameter(1)
Conditions Typ. Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
NOTE:
2558 tbl 02
1. This parameter is guaranteed by characterization data and not tested.
NOTES:
2558 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
7.10
2
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Test Conditions(1)
Guaranteed Logic HIGH Level
Symbol
VIH
Parameter
Input HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
VCC = Max.
IIL
Input LOW Current
Max.
—
—
—
0.8
V
—
5
µA
VI = 2.7V
—
—
5(4)
VI = 0.5V
—
—
–5(4)
VI = GND
—
—
–5
Clamp Diode Voltage
Vcc = Min., IN = –18mA
Short Circuit Current
Vcc = Max.(3), VO = GND
VOH
Output HIGH Voltage
Vcc = 3V, VIN = VLC or VHC, IOH = –32µA
—
–0.7
–1.2
V
–60
–120
—
mA
V
VHC
VCC
—
Vcc = Min.
IOH = –300µA
VHC
VCC
—
VIN = VIH or VIL
IOH = –12mA MIL.
2.4
4.3
—
IOH = –15mA COM’L.
2.4
4.3
—
—
GND
VLC
—
GND
VLC(4)
Vcc = 3V, VIN = VLC or VHC, IOL = 300µA
IOL = 300µA
Vcc = Min.
VIN = VIH or VIL
IOL = 32mA MIL.
—
0.3
0.5
IOL = 48mA COM’L.
—
0.3
0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.10
Unit
V
—
VIK
Output LOW Voltage
Typ.(2)
—
VI = VCC
IOS
VOL
Min.
2.0
V
2558 tbl 03
3
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
ICC
Quiescent Power Supply Current
Vcc = Max.
VIN ≥ VHC; VIN ≤ VLC
—
0.2
1.5
mA
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
ICCD
Dynamic Power Supply Current(4)
Vcc = Max.
Outputs Open
= VCC
One Input Toggling
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
—
0.15
0.25
mA/MHz
Vcc = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
= VCC
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
1.7
4.0
mA
VIN = 3.4V
VIN = GND
—
2.2
6.0
Vcc = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
= VCC
Eight Bits Toggling
fi = 2.5MHz
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
4.0
7.8(5)
VIN = 3.4V
VIN = GND
—
6.2
16.8(5)
MR
IC
Total Power Supply Current(6)
MR
MR
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.10
2558 tbl 04
4
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273
Com’l.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Clock to Output
tPHL
(1)
Condition
CL = 50 pF
RL = 500Ω
(2)
Mil.
(2)
Com’l.
(2)
Mil.
(2)
Com’l.
(2)
Mil.
Max. Min.
(2)
Max. Unit
Max. Min.
Max. Min.
Max.
Min.
13.0
2.0
15.0
2.0
7.2
2.0
8.3
2.0
5.8
2.0
6.5
ns
Propagation Delay
to Output
MR
2.0
13.0
2.0
15.0
2.0
7.2
2.0
8.3
2.0
6.1
2.0
6.8
ns
tSU
Set-up Time HIGH
or LOW Data to CP
3.0
—
3.5
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
tH
Hold Time HIGH
or LOW Data to CP
2.0
—
2.0
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tW
Clock Pulse Width
HIGH or LOW
7.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
7.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
4.0
—
5.0
—
2.0
—
2.5
—
2.0
—
2.5
—
ns
MR Pulse Width
Max. Min.
IDT54/74FCT273C
2.0
tW
Min.
IDT54/74FCT273A
LOW
tREM
Recovery Time
to CP
MR
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2558 tbl 07
7.10
5
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
SET-UP, HOLD AND RELEASE TIMES
Closed
All Other Tests
Open
3V
1.5V
0V
tH
TIMING
INPUT
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
tW
t REM
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
Open Drain
Disable Low
Enable Low
PULSE WIDTH
DATA
INPUT
ASYNCHRONOUS CONTROL
Switch
DEFINITIONS:
2558 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
CL
t SU
Test
t SU
1.5V
3V
1.5V
0V
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
1.5V
SAME PHASE
INPUT TRANSITION
t PLH
t PHL
CONTROL
INPUT
t PZL
0V
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t PZH
VOH
1.5V
OUTPUT
VOL
t PLH
t PHL
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
1.5V
0V
t PLZ
3.5V
3.5V
1.5V
0.3V
V OL
t PHZ
0.3V
1.5V
0V
V OH
0V
0V
NOTES
2558 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.10
6
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
Temperature
Range
FCT
X
X
X
Device
Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
273
273A
273C
Octal D Flip-Flop w/Clear
Fast Octal D Flip-Flop w/Clear
Super Fast Octal D Flip-Flop w/Clear
54
74
–55°C to +125°C
0°C to +70°C
2558 drw 03
7.10
7
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