IDT IDT54FCT825CTE High-performance cmos bus interface register Datasheet

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT821AT/BT/CT
IDT54/74FCT823AT/BT/CT/DT
IDT54/74FCT825AT/BT/CT
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT821T/FCT823T/FCT825T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface registers are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (EN) and Clear (CLR) – ideal for parity bus
interfacing in high-performance microprogrammed systems.
The FCT825T are 8-bit buffered registers with all the FCT823T
controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They
are ideal for use as an output port requiring high IOL/IOH.
The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0
DN
EN
CLR
D
CL
Q
D
CP Q
CL
Q
CP Q
CP
OE
Y0
YN
2567 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc
6.21
6.21
AUGUST 1995
DSC-4202/5
1
1
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FCT821 10-BIT REGISTER
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
CP
D2
D3
D4
NC
D5
D6
D7
FCT823 9-BIT REGISTER
INDEX
24
23
22
21
20
19
18
17
16
15
14
13
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
CP
D2
D3
D4
NC
D5
D6
D7
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
D8
CLR
GND
NC
CP
EN
1
2
3
P24-1
4
D24-1
5
SO24-2
6 SO24-7
7 SO24-8
8
&
9 E24-1
10
11
12
Y2
Y3
Y4
NC
Y5
Y6
Y7
2567 drw 02
LCC
TOP VIEW
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
CLR
GND
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
Y2
Y3
Y4
NC
Y5
Y6
Y7
2567 drw 03
Y8
24
23
22
21
20
19
18
17
16
15
14
13
D8
D9
GND
NC
CP
Y9
Y8
1
2
3
4 P24-1
5 D24-1
6 SO24-2
7 SO24-7
SO24-8
8
&
9
E24-1
10
11
12
D1
D0
OE
NC
VCC
Y0
Y1
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
INDEX
D1
D0
OE
NC
VCC
Y0
Y1
PIN CONFIGURATIONS
LCC
TOP VIEW
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
INDEX
CLR
GND
24
1
23
2
22
3
4 P24-1 21
5 D24-1 20
6 SO24-2 19
7 SO24-8 18
&
17
8
E24-1
16
9
10
15
14
11
12
13
VCC
OE3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
EN
CP
D1
D2
D3
NC
D4
D5
D6
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
D7
CLR
GND
NC
CP
EN
Y7
OE1
OE2
D0
D1
D2
D3
D4
D5
D6
D7
D0
OE2
OE1
NC
VCC
OE3
Y0
FCT825 8-BIT REGISTER
Y1
Y2
Y3
NC
Y4
Y5
Y6
2567 drw 04
LCC
TOP VIEW
DIP/SOIC/QSOP/CERPACK
TOP VIEW
6.21
2
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Names
DI
I/O
I
CLR
I
CP
I
YI
O
EN
I
OE
I
Description
The D flip-flop data inputs.
Inputs
When the clear input is LOW and OE is
LOW, the QI outputs are LOW. When
the clear input is HIGH, data can be
entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-toHIGH transition.
The register 3-state outputs.
Clock Enable. When the clock enable is
LOW, data on the D I input is transferred
to the QI output on the LOW-to-HIGH
clock transition. When the clock enable
is HIGH, the QI outputs do not change
state, regardless of the data or clock
input transitions.
Output Control. When the OE input is
HIGH, the Y I outputs are in the highimpedance state. When the OE input is
LOW, the TRUE register data is present
at the YI outputs.
Internal/
Outputs
QI
YI
OE
CLR
EN
DI
CP
H
H
H
H
L
L
L
H
↑
↑
L
H
Z
Z
H
L
H
L
H
H
L
L
L
L
H
H
H
H
H
H
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
↑
↑
↑
L
L
NC
NC
L
H
L
H
Z
L
Z
NC
Z
Z
L
H
Function
High Z
Clear
Hold
Load
NOTE:
1. H = HIGH
L = LOW
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition
Z = High Impedance
2567 tbl 02
2567 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
(2)
VTERM
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
–0.5 to
with Respect to
VCC +0.5
GND
TA
Operating
0 to +70
Temperature
TBIAS
Temperature
–55 to +125
Under Bias
TSTG
Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
Military
–0.5 to +7.0
Unit
V
–0.5 to
VCC +0.5
V
–55 to +125
°C
–65 to +135
°C
–65 to +150
°C
0.5
W
I OUT
–60 to +120
mA
DC Output
Current
–60 to +120
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
6
VOUT = 0V
8
Max. Unit
10
pF
12
NOTE:
1. This parameter is measured at characterization but not tested.
pF
2567 lnk 04
2567 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.21
3
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Input LOW Level
Input HIGH
Current (4)
II L
Input LOW
Current (4)
I OZH
High Impedance Output Current
II H
I OZL
(3-State Output
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
VI = 2.7V
VCC = Max.
pins) (4)
Current (4)
II
Input HIGH
VIK
Clamp Diode Voltage
VH
Input Hysteresis
I CC
Quiescent Power Supply Current
VI = 0.5V
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
µA
VCC = Max., VI = VCC (Max.)
—
—
±1
µA
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
—
—
200
—
mV
—
0.01
1
VCC = Max., VIN = GND or VCC
mA
2567 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT821/823/825T
Symbol
VOH
VOL
Output LOW Voltage
I OS
Short Circuit Current
I OFF
Test Conditions(1)
VCC = Min.
I OH = –6mA MIL.
VIN = VIH or V IL
I OH = –8mA COM'L.
I OH = –12mA MIL.
I OH = –15mA COM'L.
VCC = Min.
I OL = 32mA MIL.
VIN = VIH or V IL
I OL = 48mA COM'L.
VCC = Max., VO = GND (3)
Parameter
Output HIGH Voltage
Input/Output Power Off
Leakage(5)
VCC = 0V, VIN or V O ≤ 4.5V
Min.
2.4
Typ.(2)
3.3
Max.
—
Unit
V
2.0
3.0
—
V
—
0.3
0.5
V
–60
–120
–225
mA
—
—
±1
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.21
µA
2567 lnk 06
4
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
ICCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current (4)
IC
Total Power Supply Current (6)
∆ICC
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
OE = EN = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP= 10MHz
50% Duty Cycle
OE = EN = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
fCP= 10MHz
50% Duty Cycle
OE = EN = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
Typ.(2)
Max.
Unit
—
0.5
2.0
mA
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
VIN = VCC
VIN = GND
—
1.5
3.5
mA
VIN = 3.4V
VIN = GND
—
2.0
5.5
VIN = VCC
VIN = GND
—
3.8
7.3 (5)
VIN = 3.4V
VIN = GND
—
6.0
16.3 (5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.21
2567 tbl 07
5
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825AT
Com'l.
Symbol
tPLH
tPHL
FCT821/823/825BT
Mil.
Com'l.
Mil.
Parameter
Condition(1)
Min.(2)
1.5
1.5
1.5
Max.
7.5
Min. (2)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
Max.
11.5
Min.(2)
Propagation Delay
CP to YI (OE = LOW)
Max.
10.0
Min.(2)
1.5
Max.
8.5
1.5
20.0
1.5
20.0
1.5
15.0
1.5
16.0
4.0
—
4.0
—
3.0
—
3.0
—
ns
Unit
ns
tSU
Set-up Time HIGH or LOW
DI to CP
tH
Hold Time HIGH or LOW
DI to CP
2.0
—
2.0
—
1.5
—
1.5
—
ns
tSU
Set-up Time HIGH or LOW
EN to CP
4.0
—
4.0
—
3.0
—
3.0
—
ns
tH
Hold Time HIGH or LOW
EN to CP
2.0
—
2.0
—
0
—
0
—
ns
tPHL
Propagation Delay, CLR to YI
1.5
14.0
1.5
15.0
1.5
9.0
1.5
9.5
ns
tREM
Recovery Time CLR to CP
6.0
—
7.0
—
6.0
—
6.0
—
ns
tW
Clock Pulse Width
HIGH or LOW
7.0
—
7.0
—
6.0
—
6.0
—
ns
6.0
—
7.0
—
6.0
—
6.0
—
ns
1.5
12.0
1.5
13.0
1.5
8.0
1.5
9.0
ns
1.5
23.0
1.5
25.0
1.5
15.0
1.5
16.0
1.5
7.0
1.5
8.0
1.5
6.5
1.5
7.0
1.5
8.0
1.5
9.0
1.5
7.5
1.5
8.0
tW
tPZH
tPZL
tPHZ
tPLZ
CLR
Pulse Width LOW
Output Enable Time OE to YI
Output Disable Time OE to Y I
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
ns
2567 tbl 08
6.21
6
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825CT
Com'l.
Symbol
tPLH
tPHL
FCT823DT
Mil.
Com'l.
Parameter
Condition(1)
Min.(2)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
1.5
1.5
Max.
7.0
Min.(2)
Propagation Delay
CP to YI (OE = LOW)
Max.
6.0
Min.(2)
1.5
Max.
5.0
1.5
12.5
1.5
13.5
1.5
8.5
3.0
—
3.0
—
2.0
—
ns
Unit
ns
tSU
Set-up Time HIGH or LOW
DI to CP
tH
Hold Time HIGH or LOW
DI to CP
1.5
—
1.5
—
1.0
—
ns
tSU
Set-up Time HIGH or LOW
EN to CP
3.0
—
3.0
—
3.0
—
ns
tH
Hold Time HIGH or LOW
EN to CP
0
—
0
—
0
—
ns
tPHL
Propagation Delay, CLR to YI
1.5
8.0
1.5
8.5
1.5
5.0
ns
tREM
Recovery Time CLR to CP
6.0
—
6.0
—
3.0
—
ns
tW
Clock Pulse Width
HIGH or LOW(3)
6.0
—
6.0
—
3.0
—
ns
6.0
—
6.0
—
3.0
—
ns
1.5
7.0
1.5
8.0
1.5
4.8
ns
1.5
12.5
1.5
13.5
1.5
9.0
1.5
6.0
1.5
6.0
1.5
4.0
1.5
6.5
1.5
6.5
1.5
4.0
tW
tPZH
tPZL
tPHZ
tPLZ
CLR
Pulse Width LOW(3)
Output Enable Time OE to YI
Output Disable Time OE to Y I
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
ns
2567 tbl 09
6.21
7
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
V CC
7.0V
500Ω
Pulse
Generator
Switch
Open Drain
Disable Low
Closed
Enable Low
V OUT
VIN
Test
Open
All Other Tests
D.U.T.
50pF
RT
2567 lnk 10
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2567 drw 05
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2567 drw 07
3V
1.5V
0V
tH
2567 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
2567 drw 08
SWITCH
OPEN
3.5V
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
0V
tPLZ
tPZL
VOH
1.5V
VOL
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2567 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.21
8
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
Temp. Range
XXXX
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
E
L
SO
PY
Q
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
821AT
823AT
825AT
821BT
823BT
825BT
821CT
823CT
825CT
823DT
10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
8-Bit Non-Inverting Register
54
74
–55°C to +125°C
0°C to +70°C
2567 drw 10
6.21
9
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