IDT IDT7006L25JB High-speed 16k x 8 dual-port static ram Datasheet

IDT7006S/L
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in a 68-pin PGA, a 68-pin quad flatpack, a 68pin PLCC, and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
FEATURES:
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7006L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7006 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
DESCRIPTION:
The IDT7006 is a high-speed 16K x 8 Dual-Port Static
RAM. The IDT7006 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
FUNCTIONAL BLOCK DIAGRAM
OEL
OER
CEL
R/
CER
WR
WL
R/
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
BUSYR
BUSYL
(1,2)
A13L
A0L
NOTES:
1. (MASTER):
BUSY is
output;
(SLAVE):
BUSY is input.
2. BUSY outputs
and INT
outputs are
non-tri-stated
push-pull.
Address
Decoder
MEMORY
ARRAY
14
CEL
OEL
WL
Address
Decoder
(1,2)
A13R
A0R
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
R/
CER
OER
WR
R/
SEML
SEMR
(2)
INTL
M/S
INTR
(2)
2739 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.07
OCTOBER 1996
DSC-2739/5
1
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500µW from a 2V
battery.
The IDT7006 is packaged in a ceramic 68-pin PGA, a 68pin quad flatpack, a 68-pin PLCC, and a 64-pin TQFP (thin
plastic quad flatpack) . Military grade product is manufactured
in compliance with the latest revision of MIL-STD-883, Class
B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
56
15
IDT7006
J68-1
F68-1
16
17
55
54
INTL
53
52
18
19
PLCC / FLATPACK
TOP VIEW(3)
51
BUSYL
GND
M/S
50
BUSYR
21
49
INTR
22
48
23
47
24
46
25
45
A0R
A1R
A2R
A3R
A4R
N/C
A13R
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
CER
SEMR
R/
OER
WR
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2739 drw 02
I/O1L
I/O0L
20
A13L
57
14
A5L
A4L
A3L
A2L
A1L
A0L
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A5L
58
13
2
CEL
12
3
W
59
4
SEML
11
7
OEL
1 68 67 66 65 64 63 62 61
60
8
R/ L
5
CEL
WL
6
N/C
A13L
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
OEL
R/
9
10
I/O7R
N/C
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O1L
I/O0L
N/C
INDEX
SEML
PIN CONFIGURATIONS (1,2)
6.07
49
51
50
54
53
52
56
55
58
57
A3L
45
44
43
A1L
42
41
40
BUSYL
10
11
12
39
38
37
BUSYR
13
14
15
36
35
34
A1R
16
33
A4R
4
5
6
IDT7006
PN-64
7
8
9
32
A5R
A6R
A7R
29
30
31
A8R
A9R
26
27
28
A10R
A12R
A11R
23
24
25
GND
CER
A13R
SEMR
20
21
22
W
OER
R/ R
TQFP
TOP VIEW(3)
17
18
19
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the the actual part-marking.
A4L
47
46
I/O6R
I/O5R
48
I/O7R
I/O2R
VCC
I/O3R
I/O4R
59
I/O0R
I/O1R
61
60
1
2
3
64
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
63
62
INDEX
A2L
A0L
INTL
GND
M/S
INTR
A0R
A2R
A3R
2739 drw 03
2
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)(1,2)
51
11
A5L
50
A4L
48
A2L
46
44
42
A0L BUSYL M/S
49
A3L
47
A1L
45
40
38
A1R
36
A3R
43
41
39
37
GND BUSYR A0R A2R
35
A4R
34
A5R
INTR
53
A7L
52
10
55
A9L
54
09
A8L
32
A7R
33
A6R
08
56
57
A11L A10L
30
A9R
31
A8R
07
58
59
VCC A12L
06
60
61
N/C A13L
A6L
63
62
65
64
INTL
29
28
A11R A10R
IDT7006
G68-1
27
26
GND A12R
68-PIN PGA
TOP VIEW(3)
SEML CEL
05
04
OEL R/WL
03
67
66
I/O0L N/C
02
1
3
68
I/O1L I/O2L I/O4L
B
22
23
20
21
R/ R
OER
4
I/O3L I/O5L
A
25
A13R
SEMR
2
01
24
N/C
CER
W
5
7
9
11
13
15
GND I/O7L GND I/O1R VCC I/O4R
18
19
I/O7R
N/C
6
8
10
12
14
16
I/O6L VCC I/O0R I/O2R I/O3R I/O5R
17
I/O6R
C
D
E
F
INDEX
G
H
J
K
L
2739 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
CEL
Names
R/WL
OEL
CER
R/WR
OER
A0L – A13L
A0R – A13R
Address
I/O0L – I/O7L
I/O0R – I/O7R
Data Input/Output
SEML
INTL
BUSYL
SEMR
INTR
BUSYR
M/S
Chip Enable
Read/Write Enable
Output Enable
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
VCC
Power
GND
Ground
2739 tbl 01
6.07
3
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
R/W
OE
SEM
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATAIN
Write to Memory
L
H
L
H
DATAOUT
X
X
H
X
High-Z
Mode
I/O0-7
Read Memory
Outputs Disabled
NOTE:
1. A0L — A13L is not equal to A0R — A13R.
2739 tbl 02
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE
R/W
OE
SEM
I/O0-7
H
H
L
L
DATAOUT
H
u
X
L
DATAIN
L
X
X
L
—
Mode
Read Data in Semaphore Flag Data Out
Write I/O0 into Semaphore Flag
Not Allowed
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Military
Unit
Terminal Voltage –0.5 to +7.0
with Respect
to GND
–0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
IOUT
DC Output
Current
50
50
mA
VTERM(2)
Rating
Commercial
2739 tbl 03
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
Grade
Military
Commercial
GND
VCC
–55°C to +125°C
0V
5.0V ± 10%
0°C to +70°C
0V
5.0V ± 10%
2739 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTES:
2739 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM < Vcc
+ 0.5V.
Parameter
Min.
Typ.
Max. Unit
VCC
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
—
6.0(2)
V
—
0.8
V
VIL
Input Low Voltage
2.2
–0.5
(1)
NOTES:
1. VIL≥ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
2739 tbl 06
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)TQFP PACKAGE
Symbol
Parameter
Conditions(2) Max.
Unit
CIN
Input Capacitance
VIN = 3dV
9
pF
COUT
Output
Capacitance
VOUT = 3dV
10
pF
NOTES:
2739 tbl 07
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.07
4
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7006S
Symbol
Parameter
(1)
IDT7006L
Test Conditions
Min.
Max.
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to VCC
—
10
—
5
µA
CE = VIH, VOUT = 0V to VCC
—
10
—
5
µA
|ILI|
Input Leakage Current
|ILO|
Output Leakage Current
VOL
Output Low Voltage
IOL = 4mA
—
0.4
—
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
—
2.4
—
V
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
2739 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
Symbol
ICC
ISB1
ISB2
Parameter
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
(Both Ports Active)
f = fMAX(3)
Standby Current
(Both Ports — TTL
Level Inputs
ISB4
7006X15
Com'l. Only
Version Typ.(2) Max.
7006X17
Com'l. Only
Typ.(2) Max.
7006X20
7006X25
Typ.(2) Max. Typ.(2) Max. Unit
MIL.
S
L
—
—
—
—
—
—
—
—
160
150
370
320
155
145
340
280
COM.
S
L
170
160
310
260
170
160
310
260
160
150
290
240
155
145
265
220
CEL = CER = VIH
SEMR = SEML = VIH
MIL.
S
L
—
—
—
—
—
—
—
—
20
10
90
70
16
10
80
65
f = fMAX(3)
COM.
S
L
20
10
60
50
20
10
60
50
20
10
60
50
16
10
60
50
CE"A"=VIL and CE"B"=VIH(5)
MIL.
S
L
—
—
—
—
—
—
—
—
95
85
240
210
90
80
215
180
COM.
S
L
105
95
190
160
105
95
190
160
95
85
180
150
90
80
170
140
MIL.
S
L
—
—
—
—
—
—
—
—
1.0
0.2
30
10
1.0
0.2
30
10
CMOS Level Inputs) VIN > VCC - 0.2V or
VIN < 0.2V, f = 0 (4)
SEMR = SEML > VCC-0.2V
COM.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port — All
CMOS Level Inputs)
MIL.
S
—
—
—
—
90
225
85
200
—
170
—
100
—
170
80
90
200
155
75
85
170
145
140
90
140
80
130
75
120
Standby Current
(One Port — TTL
Level Inputs)
ISB3
Test
Condition
Active Port Outputs Open
f = fMAX(3)
SEMR = SEML > VIH
Full Standby Current Both Ports CEL and
(Both Ports — All
CER > VCC - 0.2V
CE"A" < 0.2V and
CE"B" > VCC - 0.2V (5)
SEMR = SEML > VCC-0.2V
L
—
COM. S 100
VIN > VCC - 0.2V or
VIN < 0.2v
L 90
Active Port Outputs Open,
f = fMAX(3)
mA
mA
mA
mA
mA
NOTES:
2739 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.).
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".
6.07
5
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont'd.) (VCC = 5.0V ± 10%)
7006X35
Symbol
ICC
ISB1
ISB2
ISB3
Test
Condition
Parameter
Typ.(2)
Max.
Typ.(2) Max.
7006X70
Mil Only
Typ.(2) Max. Unit
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
MIL.
S
L
150
140
300
250
150
140
300
250
140
130
300
250
(Both Ports Active)
f = fMAX(3)
COM’L.
S
L
150
140
250
210
150
140
250
210
—
—
—
—
Standby Current
(Both Ports — TTL
CEL = CER = VIH
SEMR = SEML = VIH
MIL.
S
L
13
10
80
65
13
10
80
65
10
8
80
65
Level Inputs)
f = fMAX(3)
COM’L.
13
10
60
50
13
10
60
50
—
—
—
—
Standby Current
CE"A"=VIL and CEL"B"=VIH(5)
S
L
MIL.
S
85
190
85
190
80
190
L
75
160
75
160
70
160
COM’L.
S
85
155
85
155
—
—
L
75
130
75
130
—
—
S
L
S
L
1.0
0.2
1.0
0.2
30
10
15
5
1.0
0.2
1.0
0.2
30
10
15
5
1.0
0.2
—
—
30
10
—
—
mA
S
80
175
80
175
75
175
mA
L
S
70
80
150
135
70
80
150
135
65
—
150
—
L
70
110
70
110
—
—
(One Port — TTL
Active Port Outputs Open,
Level Inputs)
f = fMAX(3)
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML = VIH
SEMR = SEML≥ VCC-0.2V
ISB4
Version
7006X55
MIL.
COM’L.
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML≥ VCC - 0.2V
Full Standby Current
(One Port — All
CMOS Level Inputs)
MIL.
COM’L.
VIN > VCC - 0.2V or
VIN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
mA
mA
mA
NOTES:
2739 tbl 10
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC =120mA (typ).
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B"is the opposite from port "A".
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC = 0.2V, VHC = VCC - 0.2V)(4)
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Test Condition
Min.
Typ.(1)
Max.
Unit
2.0
—
—
V
µA
VCC = 2V
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
CE ≥ VHC
MIL.
—
100
4000
VIN ≥ VHC or ≤ VLC
COM’L.
—
100
1500
SEM ≥ VHC
0
—
—
ns
tRC(2)
—
—
ns
NOTES:
1. TA = +25°C, VCC = 2V, and are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but are not production tested.
4. At Vcc = 2V input leakages are undefined
2739 tbl 11
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
VDR ≥ 2V
4.5V
tCDR
CE
tR
VDR
VIH
VIH
2739 drw 05
6.07
6
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
5V
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
1.5V
Output Reference Levels
1.5V
Output Load
1250Ω
1250Ω
DATAOUT
5ns Max.
Input Timing Reference Levels
5V
BUSY
INT
DATAOUT
775Ω
775Ω
30pF
5pF
Figures 1 and 2
2739 drw 06
2739 tbl 12
Figure 1. AC Output Test Load
Figure 2. Output Load
(5pF for tLZ, tHZ, tWZ, tOW)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT7006X15
Com'l. Only
Min. Max.
Parameter
Symbol
IDT7006X17
Com'l. Only
Min.
Max.
IDT7006X20
IDT7006X25
Min.
Max.
Min.
Max.
Unit
20
—
25
—
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
—
15
—
17
—
20
—
25
ns
tACE
Chip Enable Access Time(3)
—
15
—
17
—
20
—
25
ns
tAOE
Output Enable Access Time
—
10
—
10
—
12
—
13
ns
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(1, 2)
3
tHZ
(1, 2)
tPU
15
—
Output High-Z Time
(2)
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access Time
Symbol
3
—
3
—
3
—
ns
3
—
3
—
3
—
ns
10
—
10
—
12
—
15
ns
0
—
0
—
0
—
ns
15
10
15
Parameter
—
—
0
(2)
17
—
17
—
20
—
25
ns
10
—
10
—
10
—
ns
—
17
—
20
—
25
ns
IDT7006X35
IDT7006X55
Min.
Max.
Min.
Max.
IDT7006X70
Mil. Only
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
—
55
—
70
—
ns
tAA
Address Access Time
—
35
—
55
—
70
ns
tACE
Chip Enable Access Time(3)
—
35
—
55
—
70
ns
tAOE
Output Enable Access Time
—
20
—
30
—
35
ns
tOH
Output Hold from Address Change
3
—
3
—
3
—
ns
tLZ
(1, 2)
Output Low-Z Time
3
—
3
—
3
—
ns
tHZ
Output High-Z Time(1, 2)
—
15
—
25
—
30
ns
0
—
0
—
0
—
ns
35
—
50
—
50
ns
tPU
(2)
Chip Enable to Power Up Time
(2)
tPD
Chip Disable to Power Down Time
—
tSOP
Semaphore Flag Update Pulse (OE or SEM)
15
—
15
—
15
—
ns
tSAA
Semaphore Address Access Time
—
35
—
55
—
70
ns
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = V IH and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
6.07
2739 tbl 13
7
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDRESS
tAA (4)
tACE (4)
CE
tAOE
OE
(4)
W
R/
tLZ
tOH
(1)
DATAOUT
VALID DATA
(4)
tHZ (2)
BUSYOUT
tBDD (3, 4)
2739 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CE
ICC
tPU
tPD
50%
50%
ISB
2739 drw 08
6.07
8
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
Symbol
IDT7006X15
Com'l. Only
Min.
Max.
Parameter
IDT7006X17
Com'l. Only
Min.
Max.
IDT7006X20
IDT7006X25
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
(3)
15
—
17
—
20
—
25
—
ns
12
—
12
—
15
—
20
—
ns
tEW
Chip Enable to End-of-Write
tAW
Address Valid to End-of-Write
12
—
12
—
15
—
20
—
ns
tAS
Address Set-up Time(3)
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
12
—
12
—
15
—
20
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
10
—
10
—
15
—
15
—
ns
—
10
—
10
—
12
—
15
ns
tHZ
Output High-Z Time
(1, 2)
(4)
tDH
Data Hold Time
0
—
0
—
0
—
0
—
ns
tWZ
Write Enable to Output in High-Z(1, 2)
—
—
—
—
—
12
—
15
ns
tOW
Output Active from End-of-Write(1, 2, 4)
0
—
0
—
0
—
0
—
ns
5
—
5
—
5
—
5
—
ns
5
—
5
—
5
—
5
—
ns
tSWRD
tSPS
SEM Flag Write to Read Time
SEM Flag Contention Window
Symbol
Parameter
IDT7006X35
IDT7006X55
Min.
Max.
Min.
Max.
IDT7006X70
Mil. Only
Min.
Max.
Unit
WRITE CYCLE
35
—
55
—
70
—
ns
tEW
(3)
Chip Enable to End-of-Write
30
—
45
—
50
—
ns
tAW
Address Valid to End-of-Write
30
—
45
—
50
—
ns
tWC
Write Cycle Time
(3)
tAS
Address Set-up Time
0
—
0
—
0
—
ns
tWP
Write Pulse Width
25
—
40
—
50
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
15
—
30
—
40
—
ns
tHZ
Output High-Z Time(1, 2)
—
15
—
25
—
30
ns
0
—
0
—
0
—
ns
tDH
(4)
Data Hold Time
(1, 2)
tWZ
Write Enable to Output in High-Z
—
15
—
25
—
30
ns
tOW
Output Active from End-of-Write(1, 2, 4)
0
—
0
—
0
—
ns
5
—
5
—
5
—
ns
5
—
5
—
5
—
ns
tSWRD
tSPS
SEM Flag Write to Read Time
SEM Flag Contention Window
NOTES:
2739 tbl 14
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
6.07
9
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
(9)
tWR (3)
tWP(2)
tAS (6)
W
R/
tWZ (7)
DATAOUT
tOW
(4)
(4)
tDW
tDH
DATAIN
2739 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
tWC
ADDRESS
tAW
CE or SEM (9)
tAS(6)
tWR (3)
tEW (2)
W
R/
tDW
tDH
DATAIN
2739 drw 10
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured by +/- 500mV from steady state with the
Output Test Load (Figure 2)
8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore CE = VIH and SEM = VIL. tEW must be met for either condition.
6.07
10
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tOH
tSAA
A0-A2
SEM
tACE
tSOP
tDW
DATAIN
VALID
I/O
W
VALID ADDRESS
VALID ADDRESS
tWR
tAW
tEW
tAS
tWP
DATAOUT
VALID(2)
tDH
R/
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2739 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
(2)
SIDE
“A”
MATCH
W"A"
R/
SEM"A"
tSPS
A0"B"-A2"B"
SIDE(2) “B”
MATCH
W"B"
R/
SEM"B"
2739 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going High to R/W"B" or SEM"B" going High.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.07
11
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
IDT7006X15 IDT7006X17
Com'l. Only Com'l. Only
Min. Max. Min. Max.
Parameter
IDT7006X20
IDT7006X25
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
tAPS
Arbitration Priority Set-up Time(2)
tBAA
tBDA
tBAC
BUSY Disable to Valid Data(3
Write Hold After BUSY(5)
tWH
BUSY TIMING (M/S = VIL)
BUSY Input to Write(4)
tWB
tWH
Write Hold After BUSY(5)
tBDD
—
15
—
17
—
20
—
20
ns
—
15
—
17
—
20
—
20
ns
—
15
—
17
—
20
—
20
ns
—
15
—
17
—
17
—
17
ns
5
—
5
—
5
—
5
—
ns
—
18
—
18
—
30
—
35
ns
12
—
13
—
15
—
17
—
ns
0
—
0
—
0
—
0
—
ns
12
—
13
—
15
—
17
—
ns
—
30
—
30
—
45
—
50
ns
—
25
—
25
—
35
—
35
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
Symbol
(1)
Parameter
IDT7006X35
IDT7006X55
Min.
Max.
Min.
Max.
—
20
—
45
IDT7006X70
Mil. Only
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
(2)
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write Hold After BUSY(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
(3)
tBDD
tWH
—
45
ns
—
20
—
40
—
40
ns
—
20
—
40
—
40
ns
—
20
—
35
—
35
ns
5
—
5
—
5
—
ns
—
35
—
40
—
45
ns
25
—
25
—
25
—
ns
0
—
0
—
0
—
ns
25
—
25
—
25
—
ns
—
60
—
80
—
95
ns
—
45
—
65
—
80
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
(1)
Write Data Valid to Read Data Delay
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. "X" is part numbers indicates power rating (S or L).
6.07
2739 tbl 15
12
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
tWP
W"A"
R/
tDW
tDH
VALID
DATAIN "A"
tAPS (1)
MATCH
ADDR"B"
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD
(3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the port opposite from Port "A".
2739 drw 13
TIMING WAVEFORM OF WRITE WITH BUSY
tWP
W"A"
R/
tWB (3)
BUSY"B"
tWH (1)
W"B"
R/
(2)
2739 drw 14
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B" blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
6.07
13
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS
(2)
CE"B"
tBAC
tBDC
BUSY"B"
2739 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
tAPS
(2)
MATCHING ADDRESS "N"
ADDR"B"
tBAA
tBDA
BUSY"B"
2739 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
Parameter
IDT7006X15
Com'l. Only
Min.
Max.
IDT7006X17
Com'l. Only
Min.
Max.
IDT7006X20
IDT7006X25
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
ns
tWR
Write Recovery Time
—
0
0
—
0
—
0
—
ns
tINS
Interrupt Set Time
—
15
—
15
—
20
—
20
ns
tINR
Interrupt Reset Time
—
15
—
15
—
20
—
20
ns
IDT7006X35
Symbol
Parameter
IDT7006X55
Max.
Min.
Max.
Min.
IDT7006X70
Mil. Only
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
—
0
—
0
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
ns
tINS
Interrupt Set Time
—
25
—
40
—
50
ns
tINR
Interrupt Reset Time
—
25
—
40
—
50
ns
NOTE:
1. "X" in part numbers indicates power rating (S or L).
2739 tbl 16
6.07
14
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
tWR (4)
tAS (3)
CE"A"
W"A"
R/
tINS (3)
INT"B"
2739 drw 17
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
tAS(3)
CE"B"
OE"B"
tINR (3)
INT"B"
2739 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG(1,4)
Left Port
R/WL
L
CEL
L
OE L
X
Right Port
A13L-A0L
3FFF
INTL
X
R/WR
X
CER
X
OER
X
A13R-A0R
X
INTR
(2)
L
(3)
X
X
X
X
X
X
L
L
3FFF
X
X
X
X
L(3)
L
L
X
3FFE
X
(2)
X
X
X
X
X
X
L
L
3FFE
H
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
H
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2739 tbl 17
6.07
15
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE II —
ADDRESS BUSY ARBITRATION
Inputs
Outputs
CEL
CER
A0L-A13L
A0R-A13R
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
(1)
BUSYL
BUSYR
(1)
Function
NOTES:
2739 tbl 18
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT7006 are push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7006.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
The IDT7006 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7006 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
2739 tbl 19
writes to memory location 3FFF (HEX) and to clear the
interrupt flag (INTR), the right port must read the memory
location 3FFF. The message (8 bits) at 3FFE or 3FFF is userdefined, since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random
access memory. Refer to Truth Table for the interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is asserted when the right port
writes to memory location 3FFE (HEX) where a write is
defined as CE = R/W = VIL per the Truth Table . The left port
clears the interrupt by reading address location 3FFE access
when CER = OER = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.07
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IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
BUSYL
CE
BUSYL
BUSYR
MASTER
Dual Port
RAM
BUSYL
SLAVE
Dual Port
RAM
BUSYL
CE
SLAVE
Dual Port
RAM
BUSYL
BUSYR
CE
BUSYR
DECODER
MASTER
Dual Port
RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CE
BUSYR
BUSYR
2739 drw 19
Figure 3. Busy and chip enable routing for bothdata
widthin
and
depth
expansion with IDT7006 RAMs.
the
slave.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part in
slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 7006 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7006 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAMs array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7006 RAM the busy pin is
an output if the part is used as a master (M/S pin = H), and the
busy pin is an input if the part used as a slave (M/S pin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
6.07
SEMAPHORES
The IDT7006 is an extremely fast Dual-Port 16K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT7006 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7006s hardware semaphores, which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7006 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
17
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7006 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.
6.07
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HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7006’s Dual-Port
RAM. Say the 16K x 8 RAM was to be divided into two 8K x
8 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 8K. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain
control of the second 8K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
WRITE
D
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
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Figure 4. IDT7006 Semaphore Logic
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IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
PF
G
J
F
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
68-pin Flatpack (F68-1)
15
17
20
25
35
55
70
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
7006
128K (16K x 8) Dual-Port RAM
Speed in nanoseconds
Military Only
2739 drw 21
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