IDT IDT70T3599S-166DR High-speed 2.5v 256/128/64k x 36 synchronous dual-port static ram with 3.3v or 2.5v interface Datasheet

HIGH-SPEED 2.5V
256/128/64K x 36
IDT70T3519/99/89S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA), a 208-pin
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG is not supported on the 208pin PQFP package
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Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE1R
BE0L
BE0R
FT/PIPEL
1/0
0a 1a
0b 1b
0c 1c
0d 1d
1d 0d
1c 0c
1b 0b
1a 0a
a
b
c
d
d
c
b
a
FT/PIPER
1/0
R/WL
R/WR
CE0L
CE1L
1
1
0
0
B B B B B B B B
W W WWW W WW
0 1 2 3 3 2 1 0
L L L L R R R R
1/0
OEL
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
1/0
OER
Dout0-8_R
Dout9-17_R
D out18-26_R
D out27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
FT/PIPEL
CE0R
CE1R
,
0a 1a 0b 1b 0c 1c 0d 1d
0/1
FT/PIPER
0/1
a bc d
dcb a
256/128/64K x 36
MEMORY
ARRAY
I/O0L - I/O35L
Din_L
I/O0R - I/O35R
Din_R
CLKR
CLKL
A0L
REPEATL
ADSL
CNTENL
,
A17R(1)
A17L (1)
Counter/
Address
Reg.
Counter/
Address
Reg.
ADDR_R
ADDR_L
TDI
INTERRUPT
COLLISION
DETECTION
LOGIC
CE 0 L
CE1 L
R /WL
A0R
REPEATR
ADSR
CNTENR
CE0 R
CE1 R
JTAG
TDO
TCK
TMS
TRST
R/WR
COL L
INTL
COLR
INTR
(2)
ZZL
ZZ
CONTROL
ZZ R
(2)
LOGIC
NOTES:
1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
5666 drw 01
APRIL 2004
1
©2004 Integrated Device Technology, Inc.
DSC 5666/6
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Description:
The IDT70T3519/99/89 is a high-speed 256/128/64K x 36 bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70T3519/99/89 has been optimized for applications having unidirec-
6.42
2
Industrial and Commercial Temperature Ranges
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70T3519/99/89 can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (VDD) is at 2.5V.
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9)
70T3519/99/89BC
BC-256(7)
256-Pin BGA
Top View(8)
06/19/02
A1
NC
B1
I/O18L
C1
A2
TDI
B2
NC
C2
I/O18R I/O19L
D1
D2
A3
NC
B3
TDO
C3
A4
B4
NC
C4
VSS A16L(2)
D3
A5
A17L(1) A14L
D4
B5
A15L
C5
A13L
D5
A6
A11L
B6
A12L
C6
A10L
D6
A7
A8L
B7
A9L
C7
A7L
D7
A8
A9
BE2L
CE1L
B9
B8
BE3L
BE1L
B10
B11
C10
C11
BE0L CLKL ADSL
D9
D8
A11
OEL CNTENL
CE0L R/WL REPEATL
C9
C8
A10
D10
D11
A12
A5L
B12
A4L
C12
A6L
D12
A13
A2L
B13
A1L
C13
A3L
D13
A14
A0L
B14
VDD
C14
A15
A16
NC
NC
B16
B15
I/O17L
NC
C16
C15
OPTL I/O17R I/O16L
D14
D15
D16
I/O20R I/O19R I/O20L PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
E1
E2
E3
E4
I/O21R I/O21L I/O22L VDDQL
F1
F2
F3
F4
I/O23L I/O22R I/O23R VDDQL
G1
G2
G3
G4
I/O24R I/O24L I/O25L VDDQR
H1
H2
H3
H4
E5
VDD
F5
VDD
G5
VSS
H5
I/O26L I/O25R I/O26R VDDQR VSS
J1
J2
J3
J4
I/O27L I/O28R I/O27R VDDQL
K1
K2
K3
K4
I/O29R I/O29L I/O28L VDDQL
L1
L2
L3
L4
J5
ZZR
K5
VSS
L5
I/O30L I/O31R I/O30R VDDQR VDD
M1
M2
M3
M4
I/O32R I/O32L I/O31L VDDQR
N1
N2
N3
N4
M5
VDD
N5
E6
VDD
E7
INTL
F7
F6
NC
G6
VSS
H6
VSS
COLL
G7
VSS
H7
VSS
J7
J6
VSS
K6
VSS
L6
NC
M6
VDD
N6
VSS
K7
VSS
L7
COLR
M7
INTR
N7
E8
E9
VSS
VSS
F9
F8
VSS
VSS
G9
G8
VSS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
VSS
M9
M8
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
F12
P2
P3
P4
P5
I/O35R I/O34L TMS A16R(2) A13R
R1
I/O35L
T1
NC
R2
NC
T2
TCK
R3
TRST
T3
NC
R4
NC
T4
R5
A15R
T5
A17R(1) A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
P10
P11
BE1R BE0R CLKR ADSR
R9
R8
R10
R11
BE3R CE0R R/WR REPEATR
T8
T9
BE2R
CE1R
T10
T11
OER CNTENR
E14
E16
E15
F13
F14
F15
F16
VDD VDDQR I/O12R I/O13R I/O12L
G12
VSS
H12
VSS
J12
ZZL
K12
VSS
L12
VDD
M12
VDD
N12
I/O33L I/O34R I/O33R PIPE/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
P1
E13
VDD VDDQR I/O13L I/O14L I/O14R
P12
A6R
R12
A4R
T12
A5R
G13
G14
G15
G16
VDDQL I/O10L I/O11L I/O11R
H13
H14
VDDQL I/O9R
J13
J14
H16
H15
IO9L I/O10R
J15
J16
VDDQR I/O8R I/O7R
K13
K14
VDDQR I/O6R
L13
L14
VDDQL I/O5L
M13
M14
VDDQL I/O3R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
I/O2L
P14
K15
K16
I/O6L
L15
OPTR
T14
A0R
I/O7L
L16
I/O4R I/O5R
M16
M15
I/O3L
I/O4L
N16
N15
I/O1R I/O2R
P15
P16
I/O0L I/O0R
R14
I/O8L
I/O1L
R16
R15
NC
T15
NC
,
T16
NC
NC
5666 drw 02d
NOTES:
1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be VREFL and VREFR respectively for future HSTL device.
6.42
3
,
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9,10) (con't.)
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70T3519/99/89DR
DR-208(7)
208-Pin PQFP
Top View(8)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
VSS
I/O21L
I/O21R
I/O22L
I/O22R
VDDQR
VSS
I/O23L
I/O23R
I/O24L
I/O24R
VDDQL
VSS
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
ZZR
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
VSS
I/O33R
I/O33L
I/O34R
I/O34L
VSS
VDDQR
I/O18R
I/O18L
VSS
PL/FTL
COLL
INTL
NC
NC
A17L(1)
A16L(2)
A15L
A14L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
BE3L
BE2L
BE1L
BE0L
CE1L
CE0L
VDD
VDD
VSS
VSS
CLKL
OEL
R/WL
ADSL
CNTENL
REPEATL
A6L
A5L
A4L
A3L
A2L
A1L
A0L
VDD
VDD
NC
OPTL
I/O17L
I/O17R
VDDQR
VSS
06/19/02
I/O16L
I/O16R
I/O15L
I/O15R
VSS
VDDQL
I/O14L
I/O14R
I/O13L
I/O13R
VSS
VDDQR
I/O12L
I/O12R
I/O11L
I/O11R
VSS
VDDQL
I/O10L
I/O10R
I/O9L
I/O9R
VSS
VDDQR
VDD
VDD
VSS
VSS
ZZL
VDDQL
I/O8R
I/O8L
I/O7R
I/O7L
VSS
VDDQR
I/O6R
I/O6L
I/O5R
I/O5L
VSS
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
VSS
VDDQL
I/O35R
I/O35L
PL/FTR
NC
COLR
INTR
NC
NC
A17R(1)
A16R(2)
A15R
A14R
A13R
A12R
A11R
A10R
A9R
A8R
A7R
BE3R
BE2R
BE1R
BE0R
CE1R
CE0R
VDD
VDD
VSS
VSS
CLKR
OER
R/WR
ADSR
CNTENR
REPEATR
A6R
A5R
A4R
A3R
A2R
A1R
A0R
VDD
VSS
NC
OPTR
I/O0L
I/O0R
VDDQL
VSS
,
5666 drw 02a
NOTES:
1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to V ss (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 28mm x 28mm x 3.5mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Due to limited pin count, JTAG is not supported in the DR-208 package.
10. Pins 162 and 99 will be VREFL and VREFR respectively for future HSTL device.
6.42
4
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9) (con't.)
01/23/03
A1
A2
I/O19L I/O18L
B1
I/O20R
C1
B2
A3
V SS
B3
V SS I/O18R
C2
C3
I/O22L
E1
D2
V SS
E2
D3
COLL A16L(2) A12L
B4
TDI
C4
B5
D4
B6
A17L(1) A 13L
C5
D5
I/O21L I/O20L A15L
E3
A8
A7
A5
TDO
VDDQL I/O19R VDDQR PL/FTL INT L
D1
A6
A4
C6
A 14L
D6
A 11L
B7
A8L
B8
A9L
C7
BE2L
C8
A10L
A7L
BE1L
B9
CE0L
C9
BE 3L CE1L
D8
D7
A9
BE0L
D9
VDD
A10
VDD
B10
VSS
C10
V SS
D10
A11
A12
A13
CLKL CNTENL A4L
B11
ADSL
C11
R/WL
D11
OEL REPEATL
B12
A5L
C12
A6L
D12
A3L
B13
A1L
C13
A2L
D13
A14
A 0L
B14
NC
C14
A15
B15
C15
D15
E4
E14
E15
F1
F14
VDDQL I/O23R I/O24L
G1
G2
I/O26L V SS
H1
H2
G3
F4
VSS
VSS
G14
G4
I/O25L I/O24R
H3
J2
VDDQL VDD
K1
I/O28R
L1
K2
VSS
L2
J3
VSS
K3
I/O27R
L3
H4
70T3519/99/89BF
BF-208(7)
H14
VDD
J4
J14
ZZR
ZZL
208-Pin fpBGA
Top View(8)
K4
VSS
K14
L4
L14
I/O6R
M1
M14
M3
M4
VDDQL I/O29L I/O30R VSS
N1
N2
N3
VSS
N4
N14
P2
P3
P4
P5
P6
P7
I/O32R I/O32L VDDQR I/O35R TRST A16R(2) A12R
R1
VSS
T1
R2
R3
R4
U1
VSS
R5
R6
I/O33L I/O34R TCK A17R(1) A13R
T2
T3
T4
I/O33R I/O34L VDDQL TMS
U2
U3
U4
I/O35L PL/FTR COLR
F15
E17
E16
VSS
F16
I/O13L
F17
I/O12R I/O11L VDDQR
G15
G16
G17
H15
I/O9R
J15
VDD
K15
H16
H17
V SS
J16
L15
I/O7L
M15
T5
INTR
U5
A15R
T6
A14R
U6
A11R
R7
A9R
T7
A10R
U7
A7R
P8
A8R
R8
P9
BE1R
R9
BE 2R CE0R
T8
T9
BE3R CE1R
U8
BE0R
U9
VDD
P10
VDD
R10
VSS
T10
V SS
U10
OER
P11
P12
P13
CLKR C NTEN R A 4R
R11
ADS R
T11
R/W R
R12
A5R
T12
A6R
U12
A3R
R13
A1R
T13
A2R
U13
A 0R
P14
J17
K16
K17
L16
NC
T14
VSS
U14
VDD
V SS
L17
V SS
M16
I/O8L
M17
I/O6L I/O5R VDDQR
N15
P15
I/O2L I/O3L
R14
I/O10R
VSS VDDQR
N16
N17
I/O3R VDDQL I/O4R
I/O31L V SS I/O31R I/O30L
P1
VSS
D17
D16
I/O7R VDDQL I/O8R
I/O29R I/O28L VDDQR I/O27L
M2
C17
I/O9L VDDQL I/O10L I/O11R
VDD I/O26R VDDQR I/O25R
J1
C16
VDD I/O17R VDDQL I/O14L I/O14R
I/O12L I/O13R
F3
B17
B16
VDD I/O16R I/O15L
D14
V SS
VDDQR I/O16L I/O15R
I/O23L I/O22R VDDQR I/O21R
F2
A17
A16
OPTL I/O17L
R15
P16
I/O5L
P17
VSS
R16
I/O4L
R17
V DDQL I/O1R VDDQR
T15
I/O0R
U15
T17
T16
VSS
I/O2R
U17
U16
OPTR I/O0L
I/O1L
5666 drw 02c
NOTES:
1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to V SS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be V REFL and VREFR respectively for future HSTL device.
6.42
5
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (Input)(7)
R/WL
R/WR
Read/Write Enable (Input)
OEL
OER
Output Enable (Input)
A0L - A17L(6)
A0R - A17R(6)
Address (Input)
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
CLKL
CLKR
Clock (Input)
PL/FTL
PL/FTR
Pipeline/Flow-Through (Input)
ADSL
ADSR
Address Strobe Enable (Input)
CNTENL
CNTENR
Counter Enable (Input)
REPEATL
REPEATR
Counter Repeat(3)
BE0L - BE3L
BE0R - BE3R
Byte Enables (9-bit bytes) (Input)(7)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
OPTL
OPTR
Option for selecting V DDQX(1,2) (Input)
ZZL
ZZR
Sleep Mode pin(4) (Input)
VDD
Power (2.5V)(1) (Input)
VSS
Ground (0V) (Input)
TDI(5)
Test Data Input
TDO(5)
Test Data Output
TCK
Test Logic Clock (10MHz) (Input)
(5)
TMS
Test Mode Select (Input)
(5)
Reset (Initialize TAP Controller) (Input)
TRST
(5)
INTL
INTR
Interrupt Flag (Output)
COLL
COLR
Collision Alert (Output)
5666 tbl 01
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADS X.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Due to limited pin count, JTAG is not supported in the DR-208 package.
6. Address A17x is a NC for the IDT70T3599. Also, Addresses A17x and A16x are
NC's for the IDT 70T3589.
7. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
6
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
CLK
CE0
CE1
BE3
BE2
BE1
BE0
R/W
ZZ
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
X
↑
H
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
H
H
X
L
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
H
H
L
L
L
High-Z
High-Z
High-Z
DIN
Write to Byte 0 Only
X
↑
L
H
H
H
L
H
L
L
High-Z
High-Z
DIN
High-Z
Write to Byte 1 Only
X
↑
L
H
H
L
H
H
L
L
High-Z
DIN
High-Z
High-Z
Write to Byte 2 Only
X
↑
L
H
L
H
H
H
L
L
DIN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
↑
L
H
H
H
L
L
L
L
High-Z
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
X
↑
L
H
L
L
H
H
L
L
DIN
DIN
High-Z
High-Z
Write to Upper 2 bytes Only
X
↑
L
H
L
L
L
L
L
L
DIN
DIN
DIN
DIN
L
↑
L
H
H
H
H
L
H
L
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
↑
L
H
H
H
L
H
H
L
High-Z
High-Z
DOUT
High-Z
Read Byte 1 Only
L
↑
L
H
H
L
H
H
H
L
High-Z
DOUT
High-Z
High-Z
Read Byte 2 Only
L
↑
L
H
L
H
H
H
H
L
DOUT
High-Z
High-Z
High-Z
Read Byte 3 Only
MODE
Write to All Bytes
L
↑
L
H
H
H
L
L
H
L
High-Z
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
L
↑
L
H
L
L
H
H
H
L
DOUT
DOUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
↑
L
H
L
L
L
L
H
L
DOUT
DOUT
DOUT
DOUT
Read All Bytes
H
↑
X
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
X
X
X
X
X
X
X
X
X
H
High-Z
High-Z
High-Z
High-Z
Sleep Mode
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address Counter Control
Address
Previous
Internal
Address
Internal
Address
Used
CLK
An
X
An
↑
ADS
L(4)
(1,2)
MODE
CNTEN
REPEAT(6)
I/O(3)
X
H
DI/O (n)
H
DI/O(n+1)
Counter Enabled—Internal Address generation
External Address Blocked—Counter disab led (An + 1 reused)
(5)
X
An
An + 1
↑
X
An + 1
An + 1
↑
H
H
H
DI/O(n+1)
X
X
An
↑
X
X
L(4)
DI/O(n)
H
5666 tbl 02
L
External Address Used
Counter Set to last valid ADS load
5666 tbl 03
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE 0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
7
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Ambient
Temperature
GND
VDD
0 C to +70 C
0V
2.5V + 100mV
-40OC to +85OC
0V
2.5V + 100mV
O
Industrial
(1)
O
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
5666 tbl 04
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
V DD
Core Supply Voltage
2.4
2.5
2.6
V
V DDQ
I/O Supply Voltage (3)
2.4
2.5
2.6
V
V SS
Ground
0
0
0
V
V IH
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
1.7
____
VDDQ + 100mV (2)
V
V IH
Input High Voltage
JTAG
1.7
____
VDD + 100mV (2)
V
V IH
Input High Voltage ZZ, OPT, PIPE/FT
V DD - 0.2V
____
VDD + 100mV (2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.7
V
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
_
5666 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to Vss(0V), and V DDQX for that port must be supplied as indicated
above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
VDD
Parameter
Core Supply Voltage
(3)
VDDQ
I/O Supply Voltage
VSS
Ground
VIH
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
VIH
Input High Voltage
JTAG
VIH
Input High Voltage ZZ, OPT, PIPE/FT
_
Min.
Typ.
Max.
Unit
2.4
2.5
2.6
V
3.15
3.3
3.45
V
0
0
0
V
2.0
____
VDDQ + 150mV(2)
V
1.7
____
VDD + 100mV(2)
V
VDD - 0.2V
____
VDD + 100mV(2)
V
(1)
0.8
V
0.2
V
VIL
Input Low Voltage
-0.3
____
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
____
5666 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = V DDQ + 1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin
for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated
above.
6.42
8
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings (1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM
(VDD)
VDD Terminal Voltage
with Respect to GND
-0.5 to 3.6
VTERM(2)
(VDDQ )
VDDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to VDDQ + 0.3
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT(For VDDQ = 3.3V) DC Output Current
50
IOUT(For VDDQ = 2.5V) DC Output Current
40
V
mA
mA
5666 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance (1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
CIN
COUT(3)
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
10.5
pF
5666 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3519/99/89S
Symbol
|ILI|
|ILI|
|ILO|
VOL (3.3V)
Parameter
Test Conditions
Input Leakage Current(1)
(1,2)
JTAG & ZZ Input Leakage Current
(1,3)
Output Leakage Current
Output Low Voltage
(1)
(1)
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to VDDQ
___
10
µA
VDD = Max., V IN = 0V to VDD
___
±30
µA
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
___
10
µA
IOL = +4mA, VDDQ = Min.
___
0.4
V
V
V
VOH (3.3V)
Output High Voltage
IOH = -4mA, V DDQ = Min.
2.4
___
VOL (2.5V)
Output Low Voltage (1)
IOL = +2mA, VDDQ = Min.
___
0.4
VOH (2.5V)
Output High Voltage (1)
IOH = -2mA, V DDQ = Min.
2.0
___
V
5666 tbl 08
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.42
9
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (3) (VDD = 2.5V ± 100mV)
70T3519/99/89
S200
Com'l Only(8)
Symbol
IDD
ISB1(6)
ISB2(6)
ISB3
ISB4(6)
Izz
Parameter
Test Condition
Version
70T3519/99/89
S166
Com'l
& Ind(7)
70T3519/99/89
S133
Com'l
& Ind
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
S
375
525
320
450
260
370
IND
S
___
___
320
510
260
450
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
205
270
175
230
140
190
IND
S
___
___
175
275
140
235
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
300
375
250
325
200
250
IND
S
___
___
250
365
200
310
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V
or VIN < 0.2V, f = 0(2)
COM'L
S
5
15
5
15
5
15
IND
S
___
___
5
20
5
20
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
VIN > VDDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX(1)
COM'L
S
300
375
250
325
200
250
IND
S
___
___
250
365
200
310
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f=fMAX(1)
COM'L
S
5
15
5
15
5
15
IND
S
___
___
5
20
5
20
Unit
mA
mA
mA
mA
mA
mA
5666 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. I DD DC(f=0) = 15mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = V IL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, I SB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
7. 166MHz I-Temp is not available in the BF-208 package.
8. 200Mhz is not available in the BF-208 and DR-208 packages.
6.42
10
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
Figure 1
5666 tbl 10
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
5666 drw 03
Figure 1. AC Output Test load.
∆ tCD
(Typical, ns)
∆ Capacitance (pF) from AC Test Load
6.42
11
5666 drw 04
,
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
Symbol
Parameter
70T3519/99/89
S200
Com'l Only(5)
70T3519/99/89
S166
Com'l
& Ind(4)
70T3519/99/89
S133
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC1
Clock Cycle Time (Flow-Through)(1)
15
____
20
____
25
____
ns
tCYC2
Clock Cycle Time (Pipelined)(1)
5
____
6
____
7.5
____
ns
ns
(1)
tCH1
Clock High Time (Flow-Through)
6
____
8
____
10
____
tCL1
Clock Low Time (Flow-Through)(1)
6
____
8
____
10
____
ns
tCH2
Clock High Time (Pipelined)(2)
2
____
2.4
____
3
____
ns
tCL2
Clock Low Time (Pipelined)(1)
2
____
2.4
____
3
____
ns
tSA
Address Setup Time
1.5
____
1.7
____
1.8
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tSC
Chip Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSB
Byte Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSW
R/W Setup Time
1.5
____
1.7
____
1.8
____
ns
tHW
R/W Hold Time
0.5
____
0.5
____
0.5
____
ns
tSD
Input Data Setup Time
1.5
____
1.7
____
1.8
____
ns
tHD
Input Data Hold Time
0.5
____
0.5
____
0.5
____
ns
tSAD
ADS Setup Time
1.5
____
1.7
____
1.8
____
ns
tHAD
ADS Hold Time
0.5
____
0.5
____
0.5
____
ns
tSCN
CNTEN Setup Time
1.5
____
1.7
____
1.8
____
ns
tHCN
CNTEN Hold Time
0.5
____
0.5
____
0.5
____
ns
tSRPT
REPEAT Setup Time
1.5
____
1.7
____
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.4
____
4.4
____
4.6
ns
tOLZ(6)
Output Enable to Output Low-Z
1
____
1
____
1
____
ns
tOHZ(6)
Output Enable to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCD1
Clock to Data Valid (Flow-Through)(1)
____
10
____
12
____
15
ns
____
4.2
ns
(1)
tCD2
Clock to Data Valid (Pipelined)
3.4
____
3.6
____
tDC
Data Output Hold After Clock High
1
____
1
____
1
____
ns
tCKHZ(6)
Clock High to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCKLZ(6)
Clock High to Output Low-Z
1
____
1
____
1
____
ns
tINS
Interrupt Flag Set Time
____
7
____
7
____
7
ns
tINR
Interrupt Flag Reset Time
____
7
____
7
____
7
ns
tCOLS
Collision Flag Set Time
____
3.4
____
3.6
____
4.2
ns
tCOLR
Collision Flag Reset Time
____
3.4
____
3.6
____
4.2
ns
tZZSC
Sleep Mode Set Cycles
2
____
2
____
2
____
cycles
tZZRC
Sleep Mode Recovery Cycles
3
____
3
____
3
____
cycles
4
____
5
____
6
____
ns
Port-to-Port Delay
tCO
Clock-to-Clock Offset
tOFS
Clock-to-Clock Offset for Collision Detection
Please refer to Collision Detection Timing Table on Page 21
5666 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 and DR-208 packages.
6. Guaranteed by design (not production tested).
6.42
12
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tSB
tHB
BEn
R/W
ADDRESS
(4)
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
tOE
5666 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(1,2,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tHB
BEn
tSB
R/W
tHB
tSW tHW
tSA
(4)
ADDRESS
tHA
An
An + 1
tCD1
DATAOUT
An + 2
tCKHZ
Qn
Qn + 2 (5)
Qn + 1
tCKLZ
OE
An + 3
tDC
tOHZ
tOLZ
tDC
(1)
tOE
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
13
5666 drw 06
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read
tCH2
(1,2)
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
tCKHZ
Q0
DATAOUT(B1)
tSC
tCKHZ
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
Q3
tCKLZ
tDC
tHA
A0
ADDRESS(B2)
tCD2
Q1
tDC
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
5666 drw 07
Timing Waveform of a Multi-Device Flow-Through Read
tCH1
(1,2)
tCYC1
tCL1
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC tHC
tSC tHC
tCD1
tCD1
D0
DATAOUT(B1)
tCKHZ
tSA
(1)
tCD1
tCD1
D3
D1
tDC
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tCKLZ
tDC
(1)
D5
tCKHZ (1)
tCKLZ
(1)
tHA
A0
A1
A6
A5
A4
A3
A2
tSC tHC
CE0(B2)
tSC tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
5666 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3519/99/89 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN, and REPEAT = VIH.
6.42
14
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A"
ADDRESS"A"
tSD
DATAIN"A"
NO
MATCH
MATCH
tHD
VALID
tCO(3)
CLK"B"
tCD2
R/W"B"
ADDRESS"B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUT"B"
VALID
tDC
5666 drw 09
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + t CYC2 + t CD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,4)
CLK "A"
tSW
tHW
tSA
tHA
R/W "A"
ADDRESS "A"
tSD
DATAIN "A"
NO
MATCH
MATCH
tHD
VALID
tCO
(3)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
5666 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + t CD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
15
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
tCYC2
(OE = VIL)(2)
tCH2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
READ
NOP
(4)
WRITE
READ
5666 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) (2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Dn + 2
tCD2
(1)
Qn
DATAOUT
An + 3
An + 4
An + 5
tHD
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
5666 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
16
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = VIL)(2)
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(1)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKHZ
(5)
NOP
READ
tCKLZ
WRITE
Qn + 3
tDC
READ
5666 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
tSW tHW
R/W
(3)
An
tSA tHA
ADDRESS
An +1
DATAIN
(1)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
An + 4
tOE
tCD1
Qn
tCKLZ
tOHZ
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
5666 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
17
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance
tCH2
(1)
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5666 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5666 drw 16
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = V IH.
2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
18
(1)
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs) (1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
Timing Waveform of Counter Repeat
Dn + 4
WRITE WITH COUNTER
5666 drw 17
(2,6)
tCYC2
CLK
tSA tHA
An
ADDRESS
(3)
INTERNAL
ADDRESS
An+2
An+1
An
An+2
An
An+1
An+2
An+2
tSAD tHAD
ADS
tSW tHW
R/W
tSCN tHCN
CNTEN
REPEAT
(4)
tSRPT tHRPT
tSD tHD
DATAIN
D0
D3
D2
D1
tCD1
An
DATAOUT
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
An+1
An+2
An+2
,
ADVANCE
COUNTER
READ
An+1
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
5666 drw 18
NOTES:
1. CE 0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE 0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42
19
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Waveform of Interrupt Timing
Industrial and Commercial Temperature Ranges
(2)
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL(3)
3FFFF
tSC
CEL
tHC
(1)
tINS
INTR
tINR
CLKR
tSC
tHC
CER(1)
R/WR
ADDRESSR(3)
tSW
tHW
tSA
tHA
3FFFF
NOTES:
1. CE0 = VIL and CE 1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Truth Table III — Interrupt Flag
(1)
Left Port
CLKL
R/WL
(2)
CEL
(2)
5666 drw 19
Right Port
A17L-A0L
(3,4,5)
(2)
INTL
CLKR
R/WR
CER(2)
A17R-A0R(3,4,5)
Function
INTR
↑
L
L
3FFFF
X
↑
X
X
X
L
Set Right INTR Flag
↑
X
X
X
X
↑
H
L
3FFFF
H
Reset Right INTR Flag
↑
X
X
X
L
↑
L
L
3FFFE
X
Set Left INTL Flag
↑
H
L
3FFFE
H
↑
X
X
X
X
Reset Left INTL Flag
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE 1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A17X is a NC for IDT70T3599, therefore Interrupt Addresses are 1FFFF and 1FFFE.
4. A17X and A16X are NC's for IDT70T3589, therefore Interrupt Addresses are FFFF and FFFE.
5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
20
5666 tbl 12
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing(1,2)
Both Ports Writing with Left Port Clock Leading
CLKL
tOFS
tSA
(4)
tHA
ADDRESSL
A3
A2
A1
A0
tCOLR
tCOLS
COLL
(3)
tOFS
CLKR
tSA
tHA
(4)
ADDRESSR
A0
A3
A2
A1
tCOLR
tCOLS
COLR
5666 drw 20
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
Region 1 (ns)
(1)
Region 2 (ns)
5ns
0 - 2.8
2.81 - 4.6
6ns
0 - 3.8
3.81 - 5.6
7.5ns
0 - 5.3
5.31 - 7.1
NOTES:
1. Region 1
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
(2)
5666 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
CLKL
R/WL(1)
CEL(1)
A17L-A0L(2)
COLL
CLKR
R/WR(1)
CE R(1)
A17R-A0R(2)
COLR
Function
↑
H
L
MATCH
H
↑
H
L
MATCH
H
Both ports reading. Not a valid collision.
No flag output on either port.
↑
H
L
MATCH
L
↑
L
L
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
↑
L
L
MATCH
H
↑
H
L
MATCH
L
Right port reading, Left port writing.
Valid collision, flag output on Right port.
↑
L
L
MATCH
L
↑
L
L
MATCH
L
Both ports writing. Valid collision. Flag
output on both ports.
NOTES:
1. CE 0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
21
5666 tbl 14
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform - Entering Sleep Mode (1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode
(1,2)
An
An+1
(5)
R/W
OE
(5)
Dn
DATAOUT
Dn+1
(4)
NOTES:
1. CE1 = V IH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = V IH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
22
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Functional Description
The IDT70T3519/99/89 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3519/99/89s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 3FFFE when CEL = VIL and R/WL = VIH. Likewise, the
right port interrupt flag (INT R ) is asserted when the left
port writes to memory location 3FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 3FFFF (1FFFF
or 1FFFE for IDT70T3599 and FFFF or FFFE for IDT70T3589). The
message (36 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70T3599
and FFFF or FFFE for IDT70T3589) is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3599 and
FFFF or FFFE for IDT70T3589) are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table III for the interrupt
operation.
Collision Detection
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capture data that is in a state of transition and hence the reading port’s
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
not be a valid write from either port (it may essentially be a random
combination of the two). Therefore, the collision flag is output on both
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag (COLX) is asserted on the 2nd or 3rd rising clock
edge of the affected port following the collision, and remains low for
one cycle. Please refer to Collision Detection Timing table on Page 21.
During that next cycle, the internal arbitration is engaged in resetting
the alert flag (this avoids a specific requirement on the part of the user
to reset the alert flag). If two collisions occur on subsequent clock
cycles, the second collision may not generate the appropriate alert
Industrial and Commercial Temperature Ranges
flag. A third collision will generate the alert flag as appropriate. In the
event that a user initiates a burst access on both ports with the same
starting address on both ports and one or both ports writing during
each access (i.e., imposes a long string of collisions on contiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle. Please refer to the Collision Detection timing waveform on Page
21.Collision detection on the IDT70T3519/99/89 represents a
significant advance in functionality over current sync multi-ports, which
have no such capability. In addition to this functionality the
IDT70T3519/99/89 sustains the key features of bandwidth and
flexibility. The collision detection function is very useful in the case of
bursting data, or a string of accesses made to sequential addresses, in
that it indicates a problem within the burst, giving the user the option of
either repeating the burst or continuing to watch the alert flag to see
whether the number of collisions increases above an acceptable
threshold value. Offering this function on chip also allows users to
reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives
the user more flexibility in developing a solution.
Sleep Mode
The IDT70T3519/99/89 is equipped with an optional sleep or low
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulled low. When ZZ is pulled high, the port will enter sleep mode where
it will meet lowest possible power conditions. The sleep mode timing
diagram shows the modes of operation: Normal Operation, No Read/Write
Allowed and Sleep Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enable must be valid for one full cycle before a read will result in the output
of valid data.
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (IZZ). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
6.42
23
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT70T3519/99/89 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3519/99/89 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 72-bits or wider.
A18/A17/A16
IDT70T3519/99/89
CE0
CE1
CE0
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70T3519/99/89
IDT70T3519/99/89
CE1
IDT70T3519/99/89
CE0
CE0
Control Inputs
CE1
Control Inputs
Figure 4. Depth and Width Expansion with IDT70T3519/99/89
5666 drw 23
NOTE:
1. A18 is for IDT70T3519, A17 is for IDT70T3599, A16 is for IDT70T3589.
6.42
24
BE,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
,
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
Figure 5. Standard JTAG Timing
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics (1,2,3,4)
70T3519/99/89
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
3(1)
ns
tJF
JTAG Clock Fall Time
____
(1)
3
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
5666 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
25
5666 drw 24
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
IDT Device ID (27:12)
Description
0x0
Reserved for version number
Defines IDT part number
(1)
0x330
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Allows unique identification of device vendor as IDT
1
Indicates the presence of an ID register
5666 tbl 16
NOTE:
1. Device ID for IDT70T3599 is 0x331. Device ID for IDT70T3589 is 0x332.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
5666 tbl 17
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass register (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
SAMPLE/PRELOAD
0001
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
RESERVED
PRIVATE
0110,1110,1101
For internal use only.
5666 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
26
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BC
DR
BF
256-pin BGA (BC-256)
208-pin PQFP (DR-208)
208-pin fpBGA (BF-208)
200
166
133
Commercial Only(2)
Commercial & Industrial(1) Speed in Megahertz
Commercial & Industrial
S
Standard Power
70T3519 9Mbit (256K x 36) 2.5V Synchronous Dual-Port RAM
70T3599 4Mbit (128K x 36) 2.5V Synchronous Dual-Port RAM
70T3589 2Mbit (64K x 36) 2.5V Synchronous Dual-Port RAM
5666 drw 25
NOTES:
1. 166MHz I-Temp is not available in the BF-208 package.
2. 200Mhz is not available in the BF-208 and DR-208 packages.
IDT Clock Solution for IDT70T3519/99/89 Dual-Port
Dual-Port I/O Specitications
IDT Dual-Port
Part Number
Voltage
70T3519/99/89
2.5
Clock Specifications
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
LVTTL
8pF
40%
200
75ps
5T2010
5T9010
5T905, 5T9050
5T907, 5T9070
5666 tbl 19
6.42
27
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History:
01/23/03:
01/30/03:
04/25/03:
11/11/03:
03/30/04:
04/22/04:
Initial Datasheet
Page 1 Corrected 208-pin package from TQFP to PQFP
Page 11 Added Capacitance Derating drawing
Page 12 Changed tINS and tINR specs in AC Electrical Characteristics table
Page 10 Updated power numbers in DC Electrical Characteristics table
Page 12 Added tOFS symbol and parameter to AC Electrical Characteristics table
Page 21 Updated Collision Timing waveform
Page 22 Added Collision DetectionTiming table and footnotes
Page 26 Updated HIGHZ function in System Interface Parameters table
Page 27 Added IDT Clock Solution table
Page 22 & 23 Clarified Sleep Mode Text and Waveforms
Page 1 & 27 Removed Preliminary status
Page 6 Added another sentence to footnote 4 to recommend that boundary scan not be operated during sleep mode
CORPORATE HEADQUARTERS
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800-345-7015 or 408-727-5166
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6.42
28
for Tech Support:
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