IDT IDT70V15L20JI High-speed 3.3v 16/8k x 9 dual-port static ram Datasheet

HIGH-SPEED 3.3V
16/8K X 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V16/5S/L
Features
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial:15/20/25ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V16/5S
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V16/5L
Active: 415mW (typ.)
Standby: 660µW (typ.)
IDT70V16/5 easily expands data bus width to 18 bits or
◆
◆
◆
◆
◆
◆
◆
◆
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (+0.3V) power supply
Available in 68-pin PLCC and an 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0L- I/O8L
I/O0R-I/O8R
I/O
Control
I/O
Control
(2,3)
BUSYL
A13L(1)
A0L
(2,3)
BUSYR
Address
Decoder
MEMORY
ARRAY
14
CEL
OEL
R/WL
SEML
(3)
INTL
Address
Decoder
A13R(1)
A0R
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/WR
SEMR
(3)
INTR
5669 drw 01
NOTES:
1. A13 is a NC for IDT70V15.
2. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
AUGUST 2002
1
©2002 Integrated Device Technology, Inc.
DSC 5669/1
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PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Description
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 430mW of power.
The IDT70V16/5 is packaged in a 64-pin PLCC (Plastic Leaded
Chip Carriers) and an 80-pinTQFP (Thin Quad Flatpack).
The IDT70V16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM.
The IDT70V16/5 is designed to be used as stand-alone Dual-Port RAMs
or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more
wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
I/O1L
I/O0L
I/O8L
OEL
R/WL
SEML
CEL
N/C
A13L(1)
VDD
A12L
A11L
A10L
A9L
A8L
A7L
A6L
Pin Configurations(1,2,3,4)
08/26/02
INDEX
10
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
9
7
6
5
4
15
16
3
2
IDT70V16/5J
J68-1(5)
17
18
19
55
54
53
68-Pin PLCC
Top View(6)
52
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O7R
I/O8R
OER
R/WR
SEMR
CER
N/C
A13R(1)
VSS
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
I/O2L
I/O3L
I/O4L
I/O5L
VSS
I/O6L
I/O7L
VDD
VSS
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
8
NOTES:
1. A13 is a NC for IDT70V15.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately .95 in x .95 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not imply orientation of Part-marking.
2
6.42
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
VSS
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
5669 drw 02
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IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
NC
A13L(1)
VDD
A12L
A11L
A10L
A9L
A8L
A7L
A6L
NC
NC
72
70
69
68
67
66
65
64
63
62
75
NC
SEML
76
CEL
OEL
R/WL
I/O8L
I/O0L
08/26/02
79
78
77
I/O1L
Pin Configurations(1,2,3,4) (con't.)
61
71
74
73
INDEX
80
60
NC
2
59
A5L
I/O3L
3
58
A4L
I/O4L
4
57
A3L
I/O5L
5
56
A2L
VSS
6
55
A1L
7
54
53
A0L
INTL
52
BUSYL
51
VSS
50
49
M/S
BUSYR
NC
I/O2L
I/O6L
1
IDT70V16/5PF
PN80-1(5)
8
VDD
9
NC
10
VSS
11
I/O0R
12
I/O1R
13
48
INTR
I/O2R
14
47
A0R
VDD
15
46
I/O3R
16
45
A1R
A2R
I/O4R
17
44
A3R
I/O5R
18
43
A4R
I/O6R
19
42
NC
20
41
NC
NC
NOTES:
1. A13 is a NC for IDT70V15.
2. All V DD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
NC
39
38
A5R
NC
36
35
37
A6R
A7R
33
32
34
A9R
A8R
A10R
A11R
31
A12R
29
28
30
VSS
A13R(1)
NC
27
NC
26
CER
SEMR
R/WR
24
25
80-Pin TQFP
Top View(6)
40
I/O7L
22
23
I
21
L
I/O7R
I/O8R
OER
E
5669 drw 03
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PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OER
OEL
(1)
Output Enable
(1)
A0L - A13L
A0R - A13R
Address
I/O0L - I/O8L
I/O0R - I/O8R
Data Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power (3.3V)
GND
Ground (0V)
5669 tbl 01
NOTE:
1. A13 is a NC for IDT70V15.
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
SEM
I/O0-8
H
X
X
H
High-Z
Deselcted: Power-Down
L
L
X
H
DATAIN
Write to Memory
L
H
L
H
DATAOUT
X
X
H
X
High-Z
Mode
Read Memory
Outputs Disabled
5669 tbl 02
NOTE:
1.
Condition: A0L — A13L ≠ A0R — A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
CE
R/W
OE
SEM
I/O0-8
H
H
L
L
DATAOUT
H
↑
X
L
DATAIN
L
X
X
L
____
Mode
Read Semaphore Flag Data Out (I/O0 - I/O8)
Write I/O0 into Semaphore Flag
Not Allowed
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A 0 - A2.
4
6.42
5669 tbl 03
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IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Commercial
& Industrial
Unit
Terminal Voltage
with Respect to GND
-0.5 to +3.6
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
Industrial
TSTG
Storage Temperature
-65 to +150
o
C
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
TJN
Junction Temperature
+150
o
C
IOUT
DC Output Current
VTERM(2)
Rating
Maximum Operating
Temperature and Supply Voltage(1)
Grade
Ambient
Temperature
GND
Vcc
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
Commercial
50
5669 tbl 05
mA
5669 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VTERM must not exceed VDD + 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Recommended DC Operating
Conditions
Symbol
VDD
Supply Voltage
VSS
Ground
VIH
VIL
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
2.0
____
Input High Voltage
Input Low Voltage
-0.3
(1)
VDD+0.3
____
0.8
Conditions(2)
Max.
Unit
V IN = 3dV
9
pF
VOUT = 3dV
10
V
(2)
V
V
5669 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
Capacitance(1)(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
pF
5669 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V .
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V16/5S
Symbol
Parameter
(1)
Test Conditions
70V16/5L
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = 3.6V, VIN = 0V to VDD
___
10
___
5
µA
|ILO|
Output Leakage Currentt(1)
CE = VIH, VOUT = 0V to VDD
___
10
___
5
µA
IOL = +4mA
___
0.4
___
0.4
V
2.4
___
2.4
___
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOH = -4mA
5669 tbl 08
NOTE:
1. At VDD < 2.0V, Input leakages are undefined.
6.42
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PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
70V16/5X15
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Typ. (2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
mA
COM'L
S
L
150
140
215
185
140
130
200
175
130
125
190
165
IND
S
L
____
____
225
195
____
____
140
130
____
____
____
____
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
MIL &
IND
S
L
____
____
45
40
____
____
20
15
____
____
____
____
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
MIL &
IND
S
L
____
____
130
115
____
____
80
75
____
____
____
____
Both Ports CEL and
CER > VDD - 0.2V,
V IN > V DD - 0.2V or
V IN < 0.2V, f = 0 (4)
SEMR = SEML > VDD - 0.2V
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
MIL &
IND
S
L
____
____
15
5
____
____
1.0
0.2
____
____
____
____
CE"A" < 0.2V and
CE"B" > V DD - 0.2V(5)
SEMR = SEML > VDD - 0.2V
V IN > V DD - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
MIL &
IND
S
L
____
____
____
____
80
75
130
115
____
____
____
____
CER and CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
mA
mA
mA
mA
5669 tbl 09
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Output Loads and AC Test
Conditions
Input Pulse Levels
Input Rise/Fall Times
3.3V
3.3V
GND to 3.0V
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
590Ω
590Ω
DATAOUT
BUSY
INT
Figures 1 and 2
DATAOUT
435Ω
30pF
435Ω
5pF*
5669 tbl 10
,
5669 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test
Load
(for t LZ, tHZ , tWZ, tOW)
*Including scope and jig.
Timing of Power-Up / Power-Down
CE
tPU
tPD
ICC
50%
50%
ISB
5669 drw 07
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IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V16/5X15
Com'l Only
Symbol
Parameter
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
tACE
Chip Enable Access Time (3)
____
15
____
20
____
25
ns
tABE
Byte Enable Access Time (3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time (3)
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
3
____
3
____
3
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
(1,2)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time(1,2)
tPU
Chip Enable to Power Up Time (1,2)
tPD
Chip Disable to Power Down Time (1,2)
____
15
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
10
____
ns
15
____
20
____
25
ns
tSAA
Semaphore Address Access
(3)
____
5669 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = V IL.
4. 'X' in part number indicates power rating (S or L).
Waveform of Read Cycles(5)
tRC
ADDR
(4)
CE
tAA
(4)
tACE
tAOE
(4)
OE
R/W
tLZ
tOH
(1)
(4)
DATAOUT
VALID DATA
tHZ
(2)
BUSYOUT
tBDD(3,4)
5669 drw 06
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD .
5. SEM = VIH.
6.42
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PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V16/5X15
Com'l Only
Symbol
Parameter
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
15
____
20
____
25
____
ns
tEW
Chip Enable to End-of-Write(3)
12
____
15
____
20
____
ns
tAW
Address Valid to End-of-Write
12
____
15
____
20
____
ns
tAS
Address Set-up Time (3)
0
____
0
____
0
____
ns
tWP
Write Pulse Width
12
____
15
____
20
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
15
____
15
____
ns
tHZ
Output High-Z Time(1,2)
____
10
____
12
____
15
ns
tDH
Data Hold Time(4)
0
____
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1,2)
____
10
____
12
____
15
ns
tOW
Output Active from End-of-Write(1,2,4)
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
5669 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltageand temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
8
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IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ (7)
OE
tAW
CE or SEM
(9)
tWP (2)
tAS (6)
tWR
(3)
R/W
tLZ
DATAOUT
tWZ (7)
tOW
(4)
(4)
tDW
tDH
DATAIN
5669 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tEW (2)
tWR
(3)
R/W
tDW
tDH
DATAIN
5669 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP ) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + t DW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP .
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
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IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
VALID ADDRESS
VALID ADDRESS
A0-A2
tWR
tAW
tACE
tEW
SEM
tOH
tDW
DATAIN
VALID
I/O
tAS
tWP
tSOP
DATAOUT
VALID(2)
tDH
R/W
tAOE
tSWRD
OE
Read Cycle
Write Cycle
5669 drw 10
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.
Timing Waveform of Semaphore Write Condition(1,3,4)
A0"A"-A2 "A"
SIDE
(2)
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2 "B"
SIDE
(2)
"B"
MATCH
R/W"B"
SEM"B"
5669 drw 11
NOTES:
1. DOR = DOL =VIH, CE R = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM “A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
10
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High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V16/5X15
Com'l Ony
Symbol
Parameter
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
ns
tBAC
BUSY Ac cess Time from Chip Enable LOW
____
15
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
____
15
____
17
____
17
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
18
____
30
____
30
ns
tWH
Write Hold After BUSY
12
____
15
____
17
____
ns
0
____
0
____
0
____
ns
12
____
15
____
17
____
ns
____
30
____
45
____
50
ns
25
____
35
____
35
(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
____
ns
5669 tbl 13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or t DDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDH
tDW
VALID
DATAIN "A"
tAPS
(1)
MATCH
ADDR"B"
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY “A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
6.42
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5669 drw 12
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IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Timing Waveform of Write with BUSY(3)
tWP
R/W"A"
tWB
BUSY"B"
tWH
R/W"B"
(1)
(2)
5669 drw 13
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS (2)
CE"B"
tBAC
tBDC
BUSY"B"
5669 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
tAPS
(2)
ADDR"B"
Y
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
5669 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
12
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High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70V16/5X15
Com 'l Only
Sym bol
Param eter
70V16/5X20
Com 'l
& Ind
70V16/5X25
Com 'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tA S
A d d re ss Se t-up Tim e
0
____
0
____
0
____
ns
tW R
Write Re co ve ry Tim e
0
____
0
____
0
____
ns
tIN S
Inte rrup t S e t Tim e
____
15
____
20
____
20
ns
Inte rrup t Re se t Tim e
____
15
____
20
____
20
tIN R
ns
5669 tb l 1 4
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS
tAS
(2)
(3)
tWR
(4)
CE"A"
R/W"A"
tINS
(3)
INT"B"
5669 drw 16
tRC
ADDR"B"
INTERRUPT CLEAR ADDRESS
tAS
(2)
(3)
CE"B"
OE"B"
tINR
(3)
INT"B"
5669 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
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Truth Table III — Interrupt Flag(1)
Left Port
Right Port
R/WL
CEL
OEL
A13L-A0L
INTL
R/WR
CER
OER
A13R-A0R
INTR
Function
L
L
X
3FFF(4)
X
X
X
X
X
L(2)
Set Right INTR Flag
X
X
X
X
X
X
L
L
3FFF(4)
H(3)
Reset Right INTR Flag
X
X
X
X
L(3)
L
L
X
3FFE(4)
X
Set Left INTL Flag
X
L
L
3FFE(4)
H(2)
X
X
X
X
X
Reset Left INTL Flag
5669 tbl 15
NOTES:
1. Assumes BUSY L = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A13 is a NC for IDT70V15, therefore Interrupt Addresses are 1FFF and 1FFE.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
CEL
CER
AOL-A13L
AOR-A13R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
5669 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT70V16/5 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A13 a NC for IDT70V15, Address comparison will be for A0 - A 12.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D8 Left
D0 - D8 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V16/5.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A 0 - A2.
e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.
14
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High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
BUSY (L)
PRELIMINARY
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CE
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
MASTER
CE
Dual Port
RAM
BUSY (L) BUSY (R)
SLAVE
CE
Dual Port
RAM
BUSY (L) BUSY (R)
DECODER
E
BUSY (R)
5669 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V16/5 RAMs.
Functional Description
The IDT70V16/5 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V16/5 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
where a write is defined as the CE = R/W = VIL per Truth Table III. The
left port clears the interrupt by an address location 3FFE access when CER
=OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag
(INTR) is asserted when the left port writes to memory location 3FFF
(1FFF for IDT70V15) and to clear the interrupt flag (INTR), the right port
must access location 3FFF. The message (9 bits) at 3FFE or 3FFF (1FFE
or 1FFF for IDT70V15) is user-defined since it is in an addressable SRAM
location. If the interrupt function is not used, address locations 3FFE and
3FFF (1FFE and 1FFF for IDT70V15) are not used as mail boxes but
are still part of the random access memory. Refer to Truth Table III for the
interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
6.42
15
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70V16/5 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these RAMs are being expanded in depth, then the BUSY indication for
the resulting array requires the use of an external AND gate.
Width Expansion Busy Logic
Master/Slave Arrays
When expanding an IDT70V16/5 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the BUSY signal as a write inhibit signal. Thus on the IDT70V16/5 RAM
the BUSY pin is an output if the part is used as a master (M/S pin = H), and
the BUSY pin is an input if the part used as a slave (M/S pin = L) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted data in the
slave.
Semaphores
The IDT70V16/5 are extremely fast Dual-Port 16/8Kx9 Static RAMs
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
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completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT70V16/5 contain multiple processors or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70V16/5's hardware semaphores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70V16/5 does not use its semaphore flags to
control any resources through hardware, thus allowing the system
designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70V16/5 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out
writes from the other side is what makes semaphore flags useful in
interprocessor communications. (A thorough discussion on the use of this
feature follows shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side until the
semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
16
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PRELIMINARY
Industrial and Commercial Temperature Ranges
semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70V16/5’s Dual-Port RAM. Say the 16K x
9 RAM was to be divided into two 8K x 9 blocks which were to be dedicated
at any one time to servicing either the left or right port. Semaphore 0 could
be used to indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator for the upper
section of memory.
To take a resource, in this example the lower 8K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
WRITE
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
D
SEMAPHORE
READ
D0
WRITE
SEMAPHORE
READ
Figure 4. IDT70V16/5 Semaphore Logic
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5669 drw 19
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I
M
I
N
A
R
Y
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
J
80-pin TQFP (PN80-1)
68-pin PLCC (J68-1)
15
20
25
Commercial Only
Commercial & Industrial Speed in Nanoseconds
Commercial Only
S
L
Standard Power
Low Power
70V16
70V15
144K (16K x 9-Bit) 2.5V Dual-Port RAM
72K (8K x 9-Bit) 2.5V Dual-Port RAM
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
5669 drw 20
Datasheet Document History
08/26/02:
Initial Public Release
CORPORATE HEADQUARTERS
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Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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for Tech Support:
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[email protected]
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