IDT IDT70V7288L15PFI High-speed 3.3v 64k x 16 bank-switchable dual-ported sram with external bank select Datasheet

HIGH-SPEED 3.3V
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
IDT70V7288S/L
Features
◆
◆
◆
◆
◆
◆
64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
– Four independent 16K x 16 banks
– 1 Megabit of memory on chip
Fast asynchronous address-to-data access time: 15ns
User-controlled input pins included for bank selects
Independent port controls with asynchronous address & data
busses
Four 16-bit mailboxes available to each port for interprocessor communications; interrupt option
◆
◆
◆
◆
◆
Interrupt flags with programmable masking
Dual Chip Enables allow for depth expansion without
external logic
UB and LB are available for x8 or x16 bus matching
LVTTL-compatible, single 3.3V (±5%) power supply
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
MUX
R/WL
CE0L
CE1L
UBL
LBL
OEL
16Kx16
MEMORY
ARRAY
(BANK 0)
CONTROL
LOGIC
CONTROL
LOGIC
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O
CONTROL
I/O8R-15R
I/O0R-7R
MUX
I/O8L-15L
I/O0L-7L
A13L
A0L(1)
BA1L
BA0L
MUX
I/O
CONTROL
16Kx16
MEMORY
ARRAY
(BANK 1)
ADDRESS
DECODE
ADDRESS
DECODE
MUX
BANK
DECODE
BANK
DECODE
A13R
A0R(1)
BA1R
BA0R
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
BKSEL3(2)
BKSEL0(2)
MBSELL
INTL
BANK
SELECT
A5L(1)
A0L(1)
LBL/UBL
OEL
R/WL
CEL
MAILBOX
INTERRUPT
LOGIC
A5R(1)
A0R(1)
LBR/UBR
OER
R/WR
CER
MBSELR
INTR
4077 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox
address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.
JUNE 2000
1
©2000 Integrated Device Technology, Inc.
DSC-4077/6
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Description
The IDT70V7288 is a high-speed 64K x 16 (1M bit) Bank-Switchable Dual-Ported SRAM organized into four independent 16K x 16
banks. The device has two independent ports with separate controls,
addresses, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the
other port. Accesses by the ports into specific banks are controlled via
bank select pin inputs under the user's control. Mailboxes are provided
to allow inter-processor communications. Interrupts are provided to
indicate mailbox writes have occurred. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permits the onchip circuitry of each port to enter a very low standby power mode and
allows fast depth expansion.
The IDT70V7288 offers a maximum address-to-data access time
as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack
(TQFP).
Functionality
The IDT70V7288 is a high-speed asynchronous 64K x 16 BankSwitchable Dual-Ported SRAM, organized in four 16K x 16 banks. The
two ports are permitted independent, simultaneous access into separate banks within the shared array. There are four user-controlled
Bank Select input pins, and each of these pins is associated with a
specific bank within the memory array. Access to a specific bank is
gained by placing the associated Bank Select pin in the appropriate
state: VIH assigns the bank to the left port, and VIL assigns the bank to
the right port (See Truth Table IV). Once a bank is assigned to a
particular port, the port has full access to read and write within that
bank. Each port can be assigned as many banks within the array as
needed, up to and including all four banks.
The IDT70V7288 provides mailboxes to allow inter-processor
communications. Each port has four 16-bit mailbox registers available
to which it can write and read and which the opposite port can read
only. These mailboxes are external to the common SRAM array, and
are accessed by setting MBSEL = VIL while setting CE = VIH. Each
mailbox has an associated interrupt: a port can generate an interrupt
to the opposite port by writing to the upper byte of any one of its four
16-bit mailboxes. The interrupted port can clear the interrupt by
reading the upper byte. This read will not alter the contents of the
mailbox.
If desired, any source of interrupt can be independently masked via
software. Two registers are provided to permit interpretation of interrupts: the Interrupt Cause Register and the Interrupt Status Register.
The Interrupt Cause Register gives the user a snapshot of what has
caused the interrupt to be generated - the specific mailbox written to.
The information in this register provides post-mask signals: Interrupt
sources that have been masked will not be updated. The Interrupt
Status Register gives the user the status of all bits that could potentially
cause an interrupt regardless of whether they have been masked.
Truth Table V gives a detailed explanation of the use of these registers.
6.42
2
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
A5L
A4L
A3L
A2L
A1L
A0L
BA1L
BA0L
A12L
NC
BKSEL1
INTL
GND
GND
INTR
BKSEL2
A12R
BA0R
BA1R
A0R
A1R
A2R
A3R
A4R
A5R
Pin Configurations(1,2,3)
INDEX
2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
3
73
4
72
5
71
6
70
7
69
8
68
1
9
67
10
66
IDT70V7288PF
PN100-1(4)
11
12
13
65
64
63
100-Pin TQFP
Top View(5)
14
15
62
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O9L
I/O8L
Vcc
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
GND
I/O1L
I/O0L
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
Vcc
I/O7R
I/O8R
I/O9R
NC
A6L
A7L
A8L
A9L
A10L
A11L
A13L
NC
BKSEL0
LBL
UBL
CE0L
CE1L
MBSELL
Vcc
R/WL
OEL
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
A6R
A7R
A8R
A9R
A10R
A11R
A13R
NC
BKSEL3
LBR
UBR
CE0R
CE1R
,
MBSELR
GND
R/WR
OER
GND
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
4077 drw 02
Pin Names
A0 - A13(1,6)
(1)
Address Inputs
BA0 - BA1
Bank Address Inputs
MBSEL(1)
Mailbox Access Control Gate
BKSEL0-3(2)
Bank Select Inputs
(1)
Read/Write Enable
R/W
OE(1)
Output Enable
CE0, CE1
(1)
UB, LB(1)
Chip Enables
I/O Byte Enables
(1)
I/O0 - I/O15
Bidirectional Data Input/Output
INT(1)
Interrupt Flag (Output)(3)
VCC(4)
3.3VPower
(5)
GND
Ground
4077 tbl 01
NOTES:
1. Duplicated per port.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table IV for more details.
When changing the bank assignments, accesses of the affected banks must
be suspended. Accesses may continue uninterrupted in banks that are not
being reallocated.
3. Generated upon mailbox access.
4. All Vcc pins must be connected to power supply.
5. All GND pins must be connected to ground supply.
6. The first six address pins (A0-A5) for each port serve dual functions. When MBSEL
= VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve
as mailbox address inputs (A6-A13 ignored).
3
6.42
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Truth Table I – Chip Enable
CE
Industrial and Commercial Temperature Ranges
(1,2,3,4)
CE0
CE1
VIL
VIH
< 0.2V
>VCC -0.2V
Port Selected (CMOS Active)
VIH
X
Port Deselected (TTL Inactive)
X
VIL
Port Deselected (TTL Inactive)
>VCC -0.2V
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
L
H
Mode
Port Selected (TTL Active)
4077 tbl 02
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
2. Port "A" and "B" references are located where CE is used.
3. "H" = VIH and "L" = VIL.
4. CE and MBSEL cannot be active at the same time.
Truth Table II – Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
UB
LB
MBSEL
I/O8-15
I/O0-7
H
X
X
X
X
H
High-Z
High-Z
Deselected: Power-Down
(2)
(3)
(3)
Mode
X
X
X
H
H
X
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAOUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
H
L
L
L
H
DATAOUT
DATAOUT
Read Both Bytes
X(3)
X
H
X
X
X(3)
High-Z
High-Z
Outputs Disabled
4077 tbl 03
NOTES:
1. BA0L - BA1L ≠ BA0R - BA1R: cannot access same bank simultaneously from both ports.
2. Refer to Truth Table I.
3. CE and MBSEL cannot both be active at the same time.
Truth Table III – Mailbox Read/Write Control(1)
Inputs
CE
(2)
R/W
OE
Outputs
UB
LB
MBSEL
I/O8-15
I/O0-7
Mode
H
H
L
X
X
L
DATAOUT
DATAOUT
Read Data from Mailbox, ↓ clears interrupt
H
H
L
L
L
L
DATAOUT
DATAOUT
Read Data from Mailbox, ↓ clears interrupt
L
DATAIN
DATAIN
L
____
____
H
L
L
X
X
X
(3)
(3)
L
X
(3)
(3)
L
X
Write Data into Mailbox
Not Allowed
4077 tbl 04
NOTES:
1. There are four mailbox locations per port written to and read from all the I/O's (I/O0-I/O15). These four mailboxes are addressed by A0-A5. Refer to Truth Table V.
2. Refer to Truth Table I.
3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to UB and LB appropriately.
6.42
4
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
(1)
Absolute Maximum Ratings
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
to GND
Commercial
& Industrial
Unit
-0.5 to +4.6
V
Temperature
Under Bias
-55 to +125
TSTG
Storage
Temperature
-65 to +150
IOUT
DC Output
Current
TBIAS
o
o
50
Maximum Operating Temperature
and Supply Voltage(1)
Grade
Ambient
Temperature
GND
Vcc
Commercial
0OC to +70OC
0V
3.3V + 5%
0V
3.3V + 5%
C
Symbol
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
Parameter
VCC
Supply Voltage
GND
Ground
Min.
Typ.
Max.
Unit
3.135
3.3
3.465
V
0
0
0
2.0
____
Input High Voltage
(1)
Input Low Voltage
-0.3
V
VCC +5%
____
(2)
0.8
V
V
4077 tbl 07
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 5%.
(TA = +25°C, f = 1.0mhz) TQFP Package
COUT(3)
4077 tbl 06
Recommended DC Operating
Conditions
VIL
Capacitance(1)
Input Capacitance
-40 C to +85 C
mA
VIH
CIN
O
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
4077 tbl 05
Parameter
O
Industrial
C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 5% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 5%.
Symbol
Industrial and Commercial Temperature Ranges
4077 tbl 08
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
3. COUT represents CI/O as well.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 5%)
70V7288S
Symbol
Parameter
Test Conditions
70V7288L
Min.
Max.
Min.
Max.
Unit
10
___
5
µA
5
µA
Input Leakage Current(1)
VCC = 3.465V, VIN = 0V to V CC
___
|ILO|
Output Leakage Current
CE = VIH, MBSEL = VIH, VOUT = 0V to V CC
___
10
___
VOL
Output Low Voltage
IOL = +4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
|ILI|
4077 tbl 09
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
5
6.42
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 3.3V ± 5%)
70V7288X15
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Bo th Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Test Condition
CE = VIL, Outputs Disabled
MBSEL = VIH
f = fMAX(3)
Version
70V7288X20
Com'l Only
70V7288X25
Com'l & Ind
Typ.(2)
Max.
Typ.(2)
Max.
Typ. (2)
Max.
Unit
mA
COM'L
S
L
200
200
280
230
170
170
260
210
160
160
250
200
IND
S
L
____
____
____
____
____
____
____
____
160
160
280
230
COM'L
S
L
50
50
85
60
40
40
75
50
35
35
70
45
IND
S
L
____
____
____
____
____
____
____
____
35
35
80
55
COM'L
S
L
120
120
160
140
100
100
140
120
90
90
130
110
IND
S
L
____
____
____
____
____
____
____
____
90
90
150
130
Both Ports CEL and
COM'L
CER > VCC - 0.2V
VIN > VCC - 0.2V or
IND
VIN < 0.2V, f = 0(4)
MBSELR = MBSELL > VCC - 0.2V
S
L
1.5
1.5
6
3
1.5
1.5
6
3
1.5
1.5
6
3
S
L
____
____
____
____
____
____
____
____
1.5
1.5
10
6
COM'L
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
MBSELR = MBSELL > VCC - 0.2V
IND
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled
(3)
f = fMAX
S
L
115
115
140
125
95
95
130
110
85
85
120
100
S
L
____
____
____
____
____
____
____
____
85
85
140
120
CEL = CER = VIH
MBSELR = MBSELL = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
MBSELR = MBSELL = VIH
mA
mA
mA
mA
4077 tbl 10
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Truth Table I.
6.42
6
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
AC Test Conditions
3.3V
3.3V
GND to 3.0V
Input Pulse Levels
DATAOUT
INT
1.5V
Input Timing Reference Levels
1.5V
Output Reference Levels
590Ω
590Ω
3ns Max.
Input Rise/Fall Times
DATAOUT
30pF
435Ω
5pF*
435Ω
Figures 1,2 and 3
Output Load
4077 tbl 11
4077 drw 03
Figure 1. AC Output Test Load
8
7
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
4077 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
6
5
∆ tACE/tAA
(Typical, ns)
4
3
2
1
0
-1
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
,
4077 drw 05
Figure 3. Lumped Capacitance Load Typical Derating Curve
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V7288X15
Com'l Only
Symbol
Parameter
70V7288X20
Com'l Only
70V7288X25
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
15
____
20
____
25
____
ns
Address Access Time
____
15
____
20
____
25
ns
15
____
20
____
25
ns
READ CYCLE
tRC
tAA
tACE
tABE
tAOE
tOH
tLZ
tHZ
tPU
Chip Enable Access Time
(3)
____
Byte Enable Access Time
(3)
____
15
____
20
____
25
ns
Output Enable Access Time
____
9
____
10
____
11
ns
3
____
3
____
3
____
ns
0
____
0
____
0
____
ns
____
8
____
9
____
10
ns
0
____
0
____
0
____
ns
____
15
____
20
____
25
ns
____
10
____
10
____
ns
15
____
20
____
25
Output Hold from Address Change
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
Chip Enable to Power Up Time
(2,5)
(2,5)
tPD
Chip Disable to Power Down Time
tMOP
Mailbox Flag Update Pulse (OE or MBSEL)
10
Mailbox Address Access Time
____
tMAA
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and MBSEL = VIH. To access mailbox, CE= VIH and MBSEL = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Truth Table I.
7
6.42
ns
4077 tbl 12
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Assigning the Banks via the
External Bank Selects
There are four bank select pins available on the IDT70V7288, and
each of these pins is associated with a specific bank within the memory
array. The pins are user-controlled inputs: access to a specific bank is
assigned to a particular port by setting the input to the appropriate
level. The process of assigning the banks is detailed in Truth Table IV.
Once a bank is assigned to a port, the owning port has full access to
read and write within that bank. The opposite port is unable to access
that bank until the user reassigns the port. Access by a port to a bank
which it does not control will have no effect if written, and if read
unknown values on D0-D15 will be returned. Each port can be assigned
as many banks within the array as needed, up to and including all four
banks.
The bank select pin inputs must be set at either VIH or VIL - these
inputs are not tri-statable. When changing the bank assignments,
accesses of the affected banks must be suspended. Accesses may
continue uninterrupted in banks that are not being reallocated.
Truth Table IV – Memory Bank
Assignment (CE = VIH)(2,3)
BKSEL0
BKSEL1
BKSEL2
BKSEL3
BANK AND
DIRECTION (1)
H
X
X
X
B A NK 0 LE FT
X
H
X
X
B A NK 1 LE FT
X
X
H
X
B A NK 2 LE FT
X
X
X
H
B A NK 3 LE FT
L
X
X
X
B A NK 0 RIGHT
X
L
X
X
B A NK 1 RIGHT
X
X
L
X
B A NK 2 RIGHT
X
X
X
L
B A NK 3 RIGHT
NOTES:
4077 tb l 1 3
1. Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second 16Kx16
memory spaces, Bank 2 to the third 16Kx16 memory spaces; and Bank 3 to the
fourth 16Kx16 memory spaces. 'LEFT' indicates the bank is assigned to the left
port; 'RIGHT' indicates the bank is assigned to the right port. 0-4 banks may be
assigned to either port.
2. The bank select pin inputs must be set at either VIH or VIL - these inputs are not tristatable. When changing the bank assignments, accesses of the affected banks
must be suspended. Accesses may continue uninterrupted in banks that are not
being reallocated.
3. 'H' = VIH, 'L' = VIL, 'X' = Don't Care.
Mailbox Interrupts and Interrupt
Control Registers
If the user chooses the mailbox interrupt function, four mailbox
locations are assigned to each port. These mailbox locations are
external to the memory array. The mailboxes are accessed by taking
MBSEL LOW while holding CE HIGH.
The mailboxes are 16 bits wide and controllable by byte: the
message is user-defined since these are addressable SRAM locations. An interrupt is generated to the opposite port upon writing to the
upper byte of any mailbox location. A port can read the message it has
just written in order to verify it: this read will not alter the status of the
interrupt sent to the opposite port. The interrupted port can clear the
interrupt by reading the upper byte of the applicable mailbox. This read
will not alter the contents of the mailbox. The use of mailboxes to
generate interrupts to the opposite port and the reading of mailboxes
to clear interrupts is detailed in Truth Table V.
If desired, any of the mailbox interrupts can be independently
masked via software. Masking of the interrupt sources is done in the
Mask Register. The masks are individual and independent: a port can
mask any combination of interrupt sources with no effect on the other
sources. Each port can modify only its own Mask Register. The use of
this register is detailed in Truth Table V.
Two registers are provided to permit interpretation of interrupts:
these are the Interrupt Cause Register and the Interrupt Status
Register. The Interrupt Cause Register gives the user a snapshot of
what has caused the interrupt to be generated - the specific mailbox
written to by the opposite port. The information in this register provides
post-mask signals: interrupt sources that have been masked will not
be updated. The Interrupt Status Register gives the user the status of
all bits that could potentially cause an interrupt regardless of whether
they have been masked. The use of the Interrupt Cause Register and
the Interrupt Status Register is detailed in Truth Table V.
6.42
8
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Truth Table V – Mailbox Interrupts (CE = VIH)(8,9)
MB
SEL
R/W
UB
LB
A5
A4
A3
A2
A1
A0
L
X
X
X
L
L
L
L
L
L
RESERVED (7)
L
X
X
X
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RESERVED (7)
L
(1)
(1)
(1)
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT
L
(1)
(1)
(1)
H
L
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT
L
(1)
(1)
(1)
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT
L
(1)
(1)
(1)
H
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT
↓
H
(2)
(2)
H
L
L
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT
↓
H
(2)
(2)
H
L
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT
↓
H
(2)
(2)
H
L
L
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT
↓
H
(2)
(2)
H
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT
L
(3)
(3)
(3)
H
L
H
L
L
L
(4)
(4)
(4)
(4)
(5)
(5)
(5)
(5)
(6)
(6)
(6)
(6)
X
X
X
X
MAILBOX INTERRUPT CONTROLS
L
X
X
X
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RESERVED (7)
RESERVED (7)
L
X
X
X
H
H
H
H
H
H
RESERVED (7)
RESERVED (7)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DESCRIPTION
RESERVED (7)
RESERVED (7)
4077 tbl 14
NOTES:
1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in either 8-bit or 16-bit
widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be individually masked if desired, and the status of
the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port can read its own mailboxes to verify the data written, without affecting
the interrupt which is sent to the opposite port.
2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a particular mailbox clears
the interrupt associated with that mailbox without modifying the data written. Once the address and R/W are stable, the actual clearing of the interrupt is triggered by the
transition of MBSEL from VIH to VIL.
3. This register contains the Mask Register (bits D0-D3), the Interrupt Cause Register (bits D4-D7), and the Interrupt Status Register (bits D8-D11). The controls for R/W, UB,
and LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D12-D15 are "Don't Care".
4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing VIH to the appropriate bit (D0 = Mailbox 0, D1 = Mailbox 1,
D2 = Mailbox 2, and D3 = Mailbox 3) disables the interrupt, while writing VIL enables the interrupt. All four bits in this register must be written at the same time. This
register can be read at any time to verify the mask settings. The masks are individual and independent: any single interrupt source can be masked with no effect on the
other sources. Each port can modify only its own mask settings.
5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading VOL for a specific bit (D4 = Mailbox 0, D5
= Mailbox 1, D6 = Mailbox 2, and D7 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the bit in
this register (see Note 2 for this table). This register provides post-mask information: if the interrupt source has been masked, the associated bit in this register will not
update.
6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of whether they have
been masked. Reading VOL for a specific bit (D8 = Mailbox 0, D9 = Mailbox 1, D10 = Mailbox 2, and D11 = Mailbox 3) indicates that the associated interrupt source has
generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for this table). This register provides pre-mask information:
regardless of whether an interrupt source has been masked, the associated bit in this register will update.
7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D0-D15 will be returned.
8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these registers.
9. 'L' = VIL or VOL, 'H' = VIH or VOH, 'X' = Don't Care.
9
6.42
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Waveform of Read Cycles
Industrial and Commercial Temperature Ranges
(4)
tRC
ADDR
tAA (3)
tACE (3)
(5)
CE
tAOE
(3)
OE
tABE (3)
UB, LB
R/W
tOH
tLZ (1)
DATAOUT
VALID DATA
(3)
tHZ
4077 drw 06
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tABE.
4. MBSEL = VIH.
5. Refer to Truth Table I.
Timing of Power-Up Power-Down
CE (5)
ICC
tPU
tPD
50%
50%
ISB
4077 drw 07
6.42
10
(2)
,
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V7288X15
Com'l Only
Symbol
Parameter
70V7288X20
Com'l Only
70V7288X25
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
15
____
20
____
25
____
ns
tEW
Chip Enable to End-of-Write (3)
12
____
15
____
20
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
12
____
15
____
20
____
ns
0
____
0
____
ns
____
ns
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
tBS
Bank Set-up Time
tWP
(3)
Write Pulse Width
tWR
Write Recovery Time
0
____
tDW
Data Valid to End-of-Write
12
____
15
____
20
tHZ
Output High-Z Time (1,2)
____
8
____
9
____
10
ns
0
____
0
____
0
____
ns
(4)
tDH
Data Hold Time
tWZ
Write Enable to Output in High-Z(1,2)
____
8
____
9
____
10
ns
tOW
Output Active from End-of-Write (1,2,4)
3
____
3
____
3
____
ns
5
____
5
____
5
____
ns
tMWRD
Mailbox Write to Read Time
4077 tbl 15
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,CE = VIL and MBSEL = VIH. To access mailbox, CE = VIH and MBSEL = VIL. Either condition must be valid for the entire tEW time.
Refer to Truth Tables I and III.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
11
6.42
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or
MBSEL
UB or LB
(9,10)
(9)
tAS (6)
tWP
(2)
tWR
(3)
R/W
tLZ
tWZ (7)
tOW
VALID (4)
DATAOUT
(4)
tDW
tDH
DATAIN
4077 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or MBSEL
(9,10)
(6)
tAS
UB or LB
tWR(3)
tEW (2)
(9)
R/W
tDW
tDH
DATAIN
4077 drw 09
NOTES:
1. R/W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or MBSEL or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or MBSEL LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and MBSEL = VIH. To access mailboxes, CE = VIH and MBSEL = VIL. tEW must be met for either condition.
10. Refer to Truth Table I.
6.42
12
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Right Port Read of Same Data(1,2,3)
tWC
A0L-13L
and A0R-13R
ADDRESSES MATCH
tWR
tAW
tEW
CEL
tACE
CER
tBS
BKSEL0-3
tAS
tWP
R/WL
tDW
tDH
DATAIN
VALID
I/O0L-15L
R/WR
OER
tOH
DATAOUT
VALID
tLZ
I/O0R-15R
Read Cycle
Write Cycle
tHZ
4077 drw 10
NOTES:
1. UB and LB are controlled as necessary to enable the desired byte accesses.
2. Timing for Right Port Write to Left Port Read is identical.
3. Refer to Truth Tables I and IV.
Timing Waveform of Mailbox Read after Write Timing, Either Side(1,2)
tOH
tMAA
A0-A5
VALID ADDRESS
tAW
VALID ADDRESS
tWR
tACE
tEW
MBSEL
tMOP
tDW
DATAIN
VALID
I/O0-15
tAS
tWP
DATAOUT
VALID
tDH
R/W
tMWRD
tAOE
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle), refer to Truth Table I.
2. UB and LB are controlled as necessary to enable the desired byte accesses.
13
6.42
4077 drw 11
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70V7288X15
Com'l Only
Symbol
Parameter
70V7288X20
Com'l Only
70V7288X25
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
15
____
20
____
25
ns
15
____
20
____
25
ns
tINS
tINR
Interrupt Set Time
____
Interrupt Reset Time
____
4077 tbl 16
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
Waveform of Interrupt Timing(1,5)
tWC
MAILBOX SET ADDRESS
ADDR"A"
(2)
(3)
tWR (4)
tAS
MBSEL"A"
R/W"A"
tINS(3)
INT"B"
4077 drw 12
tRC
MAILBOX CLEAR ADDRESS
ADDR"B"
tAS
(2)
(3)
MBSEL"B"
OE"B"
tINR(3)
INT"B"
4077 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table V.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Truth Tables I.
6.42
14
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT70V7288 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V7288 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are
allocated at the discretion of the user, the external controller can be set
up to drive the input signals for the various devices as required to allow
for 32-bit or wider applications.
A14(1)
IDT70V7288
Bank-Switchable
SRAM
CE0
CE1
VCC
CE0
CE1
VCC
Control Inputs
Control Inputs
IDT70V7288
Bank-Switchable
SRAM
IDT70V7288
Bank-Switchable
SRAM
IDT70V7288
Bank-Switchable
SRAM
CE1
CE0
Control Inputs
CE1
CE0
Control Inputs
4077 drw 14
Figure 4. Depth and Width Expansion with IDT70V7288
NOTE:
1. This signal is provided by external logic. It is not a bit present on the address bus.
15
6.42
BKSEL0-3
R/W
LB, UB
OE
IDT70V7288S/L
64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
100-pin TQFP (PN100-1)
15
20
25
Commercial Only
Commercial & Industrial
Commercial & Industrial
S
L
Standard Power
Low Power
70V7288
1Mbit (4 x 16K x 16) 3.3V
Bank-Switchable Dual-Ported SRAM
with External Bank Selects
,
Speed in nanoseconds
4077 drw 15
Datasheet Document History
3/8/99:
6/11/99:
9/1/99:
3/10/00:
6/8/00:
Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Page 3 Added additional notes to pin configurations
Added 15ns speed grade
Changed drawing format
Removed Preliminary
Added Industrial Temperature Ranges and removed corresponding notes
Replaced IDT logo
Page 1 Added industrial temperature note
Changed ±200mV to 0mV in notes
Page 5 Increated storage temperature parameter
Clarified TA Parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
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6.42
16
for Tech Support:
831-754-4613
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