IDT IDT70V9289L7PRFI High-speed 3.3v 64k x18/x16 synchronous pipelined dual-port static ram Datasheet

HIGH-SPEED 3.3V
64K x18/x16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9389/289L
Features:
◆
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6/7.5/9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9389/289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) and
100-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WR
UB R
R/WL
UBL
CE0L
1
0
0/1
CE1L
CE0R
1
0
0/1
CE1R
LBL
OEL
LBR
OER
FT/PIPEL
0/1
1b 0b
b a
0a 1a
1a 0a
a
0b 1b
b
0/1
FT/PIPER
I/O9R-I/O17R(1)
I/O9L-I/O17L(2)
I/O
Control
I/O
Control
I/O0R-I/O8R(1)
I/O0L-I/O8L(1)
A15R
A15L
A0L
CLKL
ADSL
CNTENL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
CNTRSTL
4856 drw 01
NOTE:
1. I/O0X - I/O7X for IDT70V9289.
2. I/O8X - I/O15 X for IDT70V9289.
APRIL 2003
1
©2003 Integrated Device Technology, Inc.
DSC-4856/3
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Description:
The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Industrial & Commercial Temperature Ranges
With an input data register, the IDT70V9389/289 has been optimized
for applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 500mW of power.
VSS
V DD
ADSL
CLKL
CNTENL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
NC
NC
NC
NC
1 28
1 27
1 26
1 25
1 24
1 23
1 22
1 21
1 20
1 19
1 18
1 17
1 16
1 15
1 14
1 13
1 12
1 11
1 10
1 09
1 08
1 07
1 06
1 05
1 04
1 03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V9389PRF
PK-128-1(4)
128-Pin TQFP
Top View(5)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
NC
NC
A9R
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
NC
CNTENR
CLKR
ADSR
A 10L
A 11L
A 12L
A 13L
A 14L
A 15L
NC
NC
L BL
UB L
CE 0L
CE 1L
C NTRST L
V DD
V SS
R/W L
O EL
FT/PIP E L
V SS
I/O 17L
I/O 16L
I/O 15L
I/O 14L
V DD
V SS
I/O 13L
03/28/03
A 10R
A 11R
A 12R
A 13R
A 14R
A 15R
NC
NC
LB R
UB R
CE 0R
CE 1R
CNTRS T R
V DD
V SS
R/W R
O ER
FT/PIP E R
V SS
I/O 17R
I/O 16R
I/O 15R
I/O 14R
V DD
V DD
I/O 13R
Pin Configuration(1,2,3)
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
I/O12R
I/O11R
V SS
NC
I/O10R
I/O9R
I/O8R
I/O7R
V DD
I/O6R
I/O5R
I/O4R
V SS
I/O3R
V DD
I/O2R
I/O1R
I/O0R
V SS
V DD
I/O0L
I/O1L
V SS
I/O2L
I/O3L
V SS
I/O4L
I/O5L
I/O6L
I/O7L
V DD
I/O8L
I/O9L
I/O10L
NC
VDD
I/O11L
I/O12L
4856 drw 02
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
A 8L
A 7L
A 6L
A 5L
A 4L
A 3L
A 2L
A 1L
A 0L
CNTENL
CLKL
ADSL
V SS
VSS
ADSR
CLK R
CNTEN R
A 0R
A1R
A2R
A3R
A 4R
A 5R
A 6R
A 7R
03/28/03
INDEX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
6
71
7
69
8
68
9
67
70
10
11
12
70V9389PF
PN100-1(4)
13
14
15
66
65
64
63
100-Pin TQFP
Top View (5)
62
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O9L
I/O 8L
V DD
I/O 7L
I/O 6L
I/O 5L
I/O 4L
I/O 3L
I/O 2L
V SS
I/O1L
I/O 0L
V SS
I/O 0R
I/O 1R
I/O 2R
I/O3R
I/O4R
I/O5R
I/O6R
VDD
I/O 7R
I/O 8R
I/O 9R
I/O10R
A9L
A10L
A11L
A12L
A13L
A14L
A15L
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
V DD
FT/PIPEL
I/O17L
I/O16L
VSS
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
NOTES:
1. All V DD pins must be connected to power supply.
2. All V SS pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
3
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
VSS
OER
FT/PIPER
I/O17R
VSS
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
4856 drw 02a
,
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
NC
NC
NC
NC
A9R
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
NC
CNTENR
CLKR
ADSR
VSS
VDD
70V9289PRF
PK-128-1(4)
128-Pin TQFP
Top View(5)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A 10L
A 11L
A 12L
A 13L
A 14L
A 15L
NC
NC
LB L
UB L
CE 0L
CE 1L
CNTRS T L
V DD
V SS
R/W L
O EL
FT/PIPE L
V SS
I/O 15L
I/O 14L
I/O 13L
I/O 12L
V DD
V SS
I/O 11L
ADSL
CLKL
CNTENL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
03/28/03
12 8
12 7
12 6
12 5
12 4
12 3
12 2
12 1
12 0
11 9
11 8
11 7
11 6
11 5
11 4
11 3
11 2
11 1
11 0
10 9
10 8
10 7
10 6
10 5
10 4
10 3
A 10R
A 11R
A 12R
A 13R
A 14R
A 15R
NC
NC
LB R
UB R
CE 0R
CE 1R
CNTRS T R
V DD
V SS
R/W R
O ER
FT/PIP E R
V SS
I/O 15R
I/O 14R
I/O 13R
I/O 12R
V DD
V DD
I/O 11R
Pin Configurations(1,2,3)(con't.)
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
4
I/O10R
I/O9R
VSS
NC
I/O8R
NC
NC
I/O7R
VDD
I/O6R
I/O5R
I/O4R
VSS
I/O3R
VDD
I/O2R
I/O1R
I/O0R
VSS
VDD
I/O0L
I/O1L
VSS
I/O2L
I/O3L
VSS
I/O4L
I/O5L
I/O6L
I/O7L
VDD
NC
NC
I/O8L
NC
V DD
I/O9L
I/O10L
4856 drw 02b
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
A8L
A7L
A 6L
A 5L
A 4L
A 3L
A2L
A 1L
A 0L
CNTEN L
CLK L
ADS L
VSS
ADS R
CLK R
CNTENR
A 0R
A 1R
A 2R
A3R
A 4R
A 5R
A 6R
A 7R
A 8R
03/28/03
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
IDT70V9289PF
PN100-1(4)
11
12
13
100-Pin TQFP
Top View(5)
14
66
65
64
63
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O9L
I/O8L
V DD
I/O 7L
I/O 6L
I/O5L
I/O4L
I/O 3L
I/O 2L
V SS
I/O IL
I/O 0L
V SS
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O 5R
I/O6R
V DD
I/O7R
I/O8R
I/O9R
NC
A9L
A10L
A11L
A12L
A13L
A14L
A15L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
VDD
R/WL
OEL
FT/PIPEL
VSS
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
NOTES:
1. All V DD pins must be connected to power supply.
2. All V SS pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
5
A9R
A10R
A11R
A12R
A13R
A14R
A15R
NC
NC
LBR
UBR
CE0R
CE1R
.
CNTRSTR
VSS
R/WR
OER
FT/PIPER
VSS
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
4856 drw 02c
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (3)
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A15L
A0R - A15R
(1)
Address
(1)
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL
CLKR
Clock
UBL
UBR
Upper Byte Select(2)
LBL
LBR
Lower Byte Select(2)
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT/PIPEL
FT/PIPER
Flow-Through / Pipeline
VDD
Power (3.3V)
VSS
Ground (0V)
4856 tbl 01
NOTE:
1. I/O0X - I/O 15X for IDT70V9289.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE 1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0(5)
CE1(5)
UB(4)
LB(4)
R/W
Upper Byte
I/O9-17(6)
Lower Byte
I/O0-8(7)
X
↑
H
X
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
↑
L
H
L
H
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
H
L
L
High-Z
DATA IN
Write to Lower Byte Only
X
↑
L
H
L
L
L
DATA IN
DATA IN
Write to Both Bytes
L
↑
L
H
L
H
H
DATAOUT
High-Z
Read Upper Byte Only
L
↑
L
H
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
↑
L
H
L
L
H
DATAOUT
DATAOUT
Read Both Bytes
H
X
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
MODE
4856 tbl 02
NOTES:
1. "H" = VIH, "L" = V IL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE 1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6. I/O8 - I/O15 for IDT70V9289.
7. I/O0 - I/O7 for IDT70V9289.
6.42
6
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS
CNTEN
CNTRST
I/O(3)
X
X
0
↑
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
An
X
An
↑
L(4)
X
H
DI/O(n)
External Address Loaded into Counter
An
Ap
Ap
↑
H
H
H
DI/O(p)
External Address Blocked—Counter disabled (Ap reused)
X
Ap
Ap + 1
↑
H
L(5)
H
DI/O(p+1)
MODE
Counter Enabled—Internal Address generation
4856 tbl 03
NOTES:
1. "H" = VIH, "L" = V IL, "X" = Don't Care.
2. CE 0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Industrial
Symbol
Ambient
Temperature(2)
GND
VDD
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
Commercial
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
4856 tbl 04
Parameter
VDD
Supply Voltage
VSS
Ground
V IH
Input High Voltage
V IL
Input Low Voltage
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
2.0
____
-0.3
(1)
V
V DD+0.3V
____
(2)
0.8
V
4856 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD +0.3V.
Capacitance(1)
Absolute Maximum Ratings(1)
Symbol
VTERM(2)
Rating
Commercial
& Industrial
Unit
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
(TA = +25°C, f = 1.0MHZ)
Symbol
CIN
TBIAS(3)
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
TJN
Junction Temperature
o
C
IOUT
DC Output Current
+150
50
V
Parameter
Input Capacitance
(3)
COUT
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
4856 tbl 07
mA
4856 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references C I/O.
6.42
7
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9389/289L
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VDD = 3.6V, VIN = 0V to VDD
___
5
µA
|ILO|
Output Leakage Current
CE = VIH or CE1 = VIL, VOUT = 0V to VDD
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
V
4856 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)
70V9389/289L6
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70V9389/289L7
Com'l Only
70V9389/289L9
Com'l & Ind
70V9389/289L12
Com'l Only
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
L
220
280
200
250
175
230
150
200
IND
L
____
____
____
____
180
240
____
____
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = V IH
f = fMAX(1)
COM'L
L
60
85
50
75
40
65
30
50
IND
L
____
____
____
____
50
70
____
____
Standby
Current (One
Port - TTL
Level Inputs)
COM'L
CE"A" = VIL and
CE"B" = V IH(5)
Active Port Outputs Disabled, IND
f=fMAX(1)
L
145
185
130
165
110
145
95
130
L
____
____
____
____
110
155
____
____
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > V DD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
L
0.4
2
0.4
2
0.4
2
0.4
2
IND
L
____
____
____
____
0.4
2
____
____
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
VIN < 0.2V, Active Port,
Outputs Disabled, f = fMAX(1)
COM'L
L
145
180
130
160
100
140
90
125
IND
L
____
____
____
____
100
155
____
____
mA
mA
mA
mA
4856 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. I DD DC(f=0) = 90mA (Typ).
5. CEX = V IL means CE 0X = V IL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
8
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1, 2, and 3
4856 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
30pF
435Ω
5pF*
435Ω
4856 drw 03
4856 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
7
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
6
5
tCD1,
tCD2
(Typical, ns)
4
3
2
1
0
-1
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
4856 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
9
.
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)
70V9389/289L6
Com'l Only
70V9389/289L7
Com'l Only
70V9389/289L9
Com'l & Ind
70V9389/289L12
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
19
____
22
____
25
____
30
____
ns
10
____
12
____
15
____
20
____
ns
(2)
6.5
____
7.5
____
12
____
12
____
ns
(2)
ns
Symbol
Parameter
tCYC1
Clock Cycle Time (Flow-Through)
tCYC2
Clock Cycle Time (Pipelined)(2)
tCH1
Clock High Time (Flow-Through)
(2)
tCL1
Clock Low Time (Flow-Through)
6.5
____
7.5
____
12
____
12
____
tCH2
Clock High Time (Pipelined)(2)
4
____
5
____
6
____
8
____
ns
tCL2
Clock Low Time (Pipelined)
(2)
4
____
5
____
6
____
8
____
ns
tR
Clock Rise Time
____
3
____
3
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
____
3
____
3
ns
tSA
Address Setup Time
3.5
____
4
____
4
____
4
____
ns
tHA
Address Hold Time
0
____
0
____
1
____
1
____
ns
tSC
Chip Enable Setup Time
3.5
____
4
____
4
____
4
____
ns
tHC
Chip Enable Hold Time
0
____
0
____
1
____
1
____
ns
tSB
Byte Enable Setup Time
3.5
____
4
____
4
____
4
____
ns
tHB
Byte Enable Hold Time
0
____
0
____
1
____
1
____
ns
tSW
R/W Setup Time
3.5
____
4
____
4
____
4
____
ns
tHW
R/W Hold Time
0
____
0
____
1
____
1
____
ns
tSD
Input Data Setup Time
3.5
____
4
____
4
____
4
____
ns
tHD
Input Data Hold Time
0
____
0
____
1
____
1
____
ns
____
4
____
4
____
4
____
ns
tSAD
ADS Setup Time
3.5
tHAD
ADS Hold Time
0
____
0
____
1
____
1
____
ns
tSCN
CNTEN Setup Time
3.5
____
4
____
4
____
4
____
ns
tHCN
CNTEN Hold Time
0
____
0
____
1
____
1
____
ns
tSRST
CNTRST Setup Time
3.5
____
4
____
4
____
4
____
ns
tHRST
CNTRST Hold Time
0
____
0
____
1
____
1
____
ns
tOE
Output Enable to Data Valid
____
6.5
____
7.5
____
9
____
12
ns
tOLZ
Output Enable to Output Low-Z(1)
2
____
2
____
2
____
2
____
ns
tOHZ
(1)
Output Enable to Output High-Z
tCD1
Clock to Data Valid (Flow-Through)(2)
(2)
tCD2
Clock to Data Valid (Pipelined)
tDC
Data Output Hold After Clock High
1
7
1
7
1
7
1
7
ns
____
15
____
18
____
20
____
25
ns
____
6.5
____
7.5
____
9
____
12
ns
2
____
2
____
2
____
2
____
ns
tCKHZ
(1)
Clock High to Output High-Z
2
9
2
9
2
9
2
9
ns
tCKLZ
Clock High to Output Low-Z(1)
2
____
2
____
2
____
2
____
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
24
____
28
____
35
____
40
ns
tCCS
Clock-to-Clock Setup Time
____
9
____
10
____
15
____
15
ns
4856 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
6.42
10
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE 0
tSC
tHC
tSB
tHB
t SC
tHC
tSB
tHB
CE1
UB, LB
R/W
tSW tHW
tSA
ADDRESS
(5)
tHA
An
An + 1
tCD1
DATAOUT
An + 3
tCKHZ (1)
Qn
tCKLZ
OE
An + 2
tDC
Qn + 1
Qn + 2
(1)
(1)
tOHZ
tDC
tOLZ (1)
(2)
..
tOE
4856 drw 06
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(4)
CE1
tSB
tSB
tHB
R/W
ADDRESS
(5)
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
Qn
tCKLZ
An + 3
tDC
tCD2
DATAOUT
OE
tHB
(6)
UB, LB
(1)
(6)
Qn + 1
tOHZ(1)
Qn + 2
tOLZ (1)
(2)
tOE
4856 drw 07
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = V IH, CE1 = VIL, UB = VIH, or LB = V IH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X' here denotes Left or Right port. The diagram is with respect to that port.
6.42
11
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
Q0
DATAOUT(B1)
tDC
tCD2
Q3
Q1
tDC
tCKLZ
(3)
tCKHZ (3)
tHA
A0
ADDRESS(B2)
tCKHZ(3)
tCD2
tCD2
tSA
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
tSC tHC
CE0(B2)
tSC
tHC
tCD2
DATAOUT(B2)
tCKHZ
(3)
Q2
tCKLZ(3)
tCD2
Q4
tCKLZ (3)
4856 drw 08
Timing Waveform with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW tHW
R/W "A"
tSA
ADDRESS "A"
tHA
tSD
DATAIN "A"
NO
MATCH
MATCH
tHD
VALID
tCCS
(6)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCWDD
(6)
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
4856 drw 09
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9389 or IDT70V9289 for this waveform, and are setup for depth expansion
in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1) , CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.42
12
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD2
(2)
tCKHZ
(1)
(1)
tCD2
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP
(5)
WRITE
READ
4856 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2
tCYC2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 4
An + 5
tSD tHD
DATAIN
Dn + 3
Dn + 2
tCD2
(2)
tCKLZ(1)
tCD2
Qn
DATAOUT
Qn + 4
tOHZ(1)
OE
READ
WRITE
READ
4856 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
13
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(2)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKHZ
(5)
NOP
READ
(1)
tCKLZ
WRITE
Qn + 3
tDC
READ
(1)
4856 drw 12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
tSW tHW
(4)
An
tSA tHA
ADDRESS
An +1
DATAIN
(2)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
Qn
An + 4
tOE
tCD1
(1)
tOHZ
tCKLZ
(1)
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
4856 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
14
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
4856 drw 14
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
4856 drw 15
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = V IH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
15
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
CNTEN(7)
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
4856 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
An
ADDRESS(4)
INTERNAL(3)
ADDRESS
Ax (6)
0
1
An + 2
An + 1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRST tHRST
CNTRST
tSD
tHD
D0
DATAIN
DATAOUT(5)
Q1
Q0
COUNTER
RESET
(6)
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
READ
ADDRESS n+1
NOTES:
4856 drw 17
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ Address is written to during this cycle.
6.42
16
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V9389/289 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operation of the address counters for fast interleaved memory applications.
CE0 = VIH or CE1 = VIL for one clock cycle will power down the internal
circuitry to reduce static power consumption. Multiple chip enables allow
easier banking of multiple IDT70V9389/289's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are
required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
The IDT70V9389/289 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
The IDT70V9389/289 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 36/32-bit
or wider applications.
A16
IDT70V9389/289 CE0
CE1
IDT70V9389/289 CE0
VDD
Control Inputs
CE1
VDD
Control Inputs
IDT70V9389/289 CE1
IDT70V9389/289 CE1
CE0
CE0
Control Inputs
Control Inputs
4856 drw 18
Figure 4. Depth and Width Expansion with IDT70V9389/289
6.42
17
CNTRST
CLK
ADS
CNTEN
R/W
LB, UB
OE
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Ordering Information
IDT
XXXXX
A
99
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I (1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PRF
PF
128-pin TQFP (PK128-1)
100-pin TQFP (PN100-1)
6
7
9
12
Commercial Only
Commercial Only
Commercial & Industrial
Commercial Only
L
Low Power
70V9389
70V9289
1152K (64K x 18-Bit) Synchronous Dual-Port RAM
1024K (64K x 16-Bit) Synchronous Dual-Port RAM
Speed in nanoseconds
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
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IDT Clock Solution for IDT70V9389/289 Dual-Port
Dual-Port I/O Specitications
Dual-Port Clock Specifications
IDT Dual-Port Part
Number
Voltage
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
70V9389/289
3.3
LVTTL
9pF
40%
100
150ps
IDT
PLL
Clock Devices
IDT
Non-PLL Clock
Devices
IDT2305
IDT2308
IDT2309
FCT3805
FCT3805D/E
FCT3807
FCT3807D/E
4856 tbl12
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IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Datasheet Document History
9/30/99:
11/12/99:
06/23/00:
04/09/03:
Initial Public Release
Replaced IDT logo
Page 3 Changed information in Truth Table II
Page 4 Increased storage temperature parameters
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
Consolidated multiple devices into one datasheet
Changed naming conventions from VCC to VDD and from GND to Vss
Page 3 & 5 Added PN-100 TQFP pin configuration
Page 1 & 18 Added PN-100 TQFP availability and ordering information
Page 2 - 5 Added date revision to pin configurations
Page 7 Added junction temperature to Absolute Maximum Ratings Table
Added Ambient Temperature footnote
Page 8, 10 & 18 Added 6ns speed grade
Page 8 Added updated DC power numbers to the DC Electrical Characteristics Table
Page 10 Added 6ns speed AC timing numbers and changed tOE to be equal to tCD2 in the AC Electrical Characteristics Table
Page 18 Added IDT Clock Solution Table
Page 1& 19 Removed "Preliminary" status
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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19
for Tech Support:
831-754-4613
[email protected]
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