IDT IDT71024S12TYGI8 Cmos static ram 1 meg (128k x 8-bit) two chip selects plus one output enable pin Datasheet

CMOS Static RAM
1 Meg (128K x 8-Bit)
Features
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IDT71024S
Description
128K x 8 advanced high-speed CMOS static RAM
Commercial (0°C to +70°C), Industrial (–40°C to +85°C)
Equal access and cycle times
— Commercial and Industrial: 12/15/20ns
Two Chip Selects plus one Output Enable pin
Bidirectional inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 300 and 400 mil Plastic SOJ.
The IDT71024 is a 1,048,576-bit high-speed static RAM organized as
128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71024 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71024 are TTL-compatible, and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32pin 400 mil Plastic SOJ.
Functional Block Diagram
FEBRUARY 2013
1
©2012 Integrated Device Technology, Inc.
DSC-2964/19
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
Absolute Maximum Ratings(1)
Symbol
Rating
Value
Terminal Voltage with Respect to GND
–0.5 to +7.0
V
TBIAS
Temperature Under Bias
–55 to +125
o
C
TSTG
Storage Temperature
–55 to +125
o
C
PT
Power Dissipation
1.25
W
IOUT
DC Output Current
50
mA
VTERM
(2)
Unit
2964 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed V CC + 0.5V.
SOJ
Top View
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Truth Table(1,3)
Parameter(1)
Symbol
Inputs
WE
CS1
CS2
OE
I/O
X
H
X
X
High-Z
Function
Deselected – Standby (ISB)
X
VHC(2)
X
X
High-Z
Deselected – Standby (ISB1)
X
X
L
X
High-Z
Deselected – Standby (ISB)
X
X
VLC(2)
X
High-Z
Deselected – Standby (ISB1)
H
L
H
H
High-Z
Outputs Disabled
H
L
H
L
DATAOUT
Read Data
L
L
H
X
DATAIN
Write Data
Input Capacitance
CI/O
I/O Capacitance
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
8
pF
2964 tbl 03
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
Recommended DC Operating
Conditions
Symbol
2964 tbl 01
NOTES:
1. H = VIH, L = VIL, X = Don't care.
2. VLC = 0.2V, VHC = VCC –0.2V.
3. Other inputs ≥VHC or ≤VLC.
CIN
Conditions
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
VIL
Temperature
GND
VCC
Commercial
0°C to +70°C
0V
5.0V ± 0.5V
Industrial
–40°C to +85°C
0V
5.0V ± 0.5V
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
VCC+0.5
V
____
0.8
(1)
–0.5
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
Recommended Operating
Temperature and Supply Voltage
Grade
Parameter
2964 tbl 05
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2
V
2964 tbl 04
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
IDT71024
Symbol
Parameter
Test Condition
Min.
Max.
Unit
|ILI|
Input Leakage Current
V CC = Max., VIN = GND to V CC
___
5
µA
|ILO|
Output Leakage Current
V CC = Max., CS1 = VIH, VOUT = GND to V CC
___
5
µA
V OL
Output Low Voltage
IOL = 8mA, VCC = Min.
___
0.4
V
VOH
Output High Voltage
IOH = –4mA, VCC = Min.
2.4
___
V
2964 tbl 06
DC Electrical Characteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
71024S12
Symbol
Parameters
71024S15
71024S20
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Unit
ICC
Dynamic Operating Current,
CS2 ≥ V IH and CS1 ≤ VIL, Outputs Open,
VCC = Max., f = fMAX(2)
160
160
155
155
140
140
mA
ISB
Standby Power Supply Current (TTL Level)
CS1 ≥ VIH or CS2 ≤ VIL, Outputs Open,
VCC = Max., f=fMAX(2)
40
40
40
40
40
40
mA
ISB1
Full Standby Power Supply Current
(CMOS Level), CS1 ≥ VHC or
CS2 ≤ V LC, Outputs Open,
VCC = Max., f = 0(2), VIN ≤ VLC or VIN ≥ VHC
10
10
10
10
10
10
mA
2964 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address
input lines are changing.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
5V
2964 tbl 08
480Ω
5V
DATA OUT
480Ω
5pF*
255Ω
DATA OUT
30pF
2964 drw 04
255Ω
*Including jig and scope capacitance.
2964 drw 03
Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ, tOLZ, tCHZ, t OHZ, tOW, and tWHZ)
6.42
3
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71024S12
Symbol
Parameter
71024S15
71024S20
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
12
—
15
—
20
—
ns
tAA
Address Access Time
—
12
—
15
—
20
ns
tACS
Chip Select Access Time
—
12
—
15
—
20
ns
tCLZ(1)
Chip Sele ct to Output in Low-Z
3
—
3
—
3
—
ns
tCHZ
Chip Desele ct to Output in High-Z
0
6
0
7
0
8
ns
tOE
Output Enable to Output Valid
—
6
—
7
—
8
ns
tOLZ(1)
Output Enab le to Output in Low-Z
0
—
0
—
0
—
ns
tOHZ(1)
Output Disab le to Output in High-Z
0
5
0
5
0
7
ns
tOH
Output Hold from Address Change
4
—
4
—
4
—
ns
tPU(1)
Chip Select to Power-Up Time
0
—
0
—
0
—
ns
tPD(1)
Chip Deselect to Power-Down Time
—
12
—
15
—
20
ns
tWC
Write Cycle Time
12
—
15
—
20
—
ns
tAW
Address Valid to End-of-Write
10
—
12
—
15
—
ns
tCW
Chip Select to End-of-Write
10
—
12
—
15
—
ns
tAS
Address Set-Up Time
0
—
0
—
0
—
ns
tWP
Write Pulse Width
8
—
12
—
15
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
7
—
8
—
9
—
ns
tDH
Data Hold Time
0
—
0
—
0
—
ns
Output Active from End-of-Write
3
—
3
—
4
—
ns
Write Enab le to Output in High-Z
0
5
0
5
0
8
ns
(1)
Write Cycle
tOW(1)
(1)
tWHZ
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
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2964 tbl 09
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
Timing Waveform of Read Cycle No. 2(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)(1,4,6)
Timing Waveform of Write Cycle No. 2
(CS1 AND CS2 Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.
2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must
both be active during the tCW write period.
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
6.42
6
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
71024
S
XX
Device
Type
Power
Speed
X
Package
X
X
Process/
Temperature
Range
X
Blank
8
Tube or Tray
Tape and Reel
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
G
Green
TY
Y
300-mil SOJ (SO32-2)
400-mil SOJ (SO32-3)
12
15
20
Speed in nanoseconds
2964 drw 09
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IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/30/99
Pg. 1, 3, 4, 7
Pg. 1–4, 7
1/6/2000
2/18/00
3/14/00
08/09/00
02/01/01
01/30/04
05/22/06
02/13/07
08/13/09
02/05/13
Pg. 3
Pg. 6
Pg. 8
Pg. 4
Pg. 3
Pg. 3
Pg. 7
Pg.3
Pg.7
Pg.2
Pg.1
Pg.7
Updated to new format
Added 12ns industrial speed grade offering
Removed military temperature offerings
Removed 17ns and 25ns speed grades
Revised ICC and ISB1 for 15ns and 20ns industrial speed grades
Removed Note 1, reordered notes and footnotes
Added Datasheet Document History
Changed tWP(min) for 12ns speed grade from 10ns to 8ns.
Revised Icc and ISB for Industrial Temperature offerings to meet commercial specifications
Revised ISB to accommodate speed functionality
Not recommended for new designs
Removed "Not recommended for new designs"
Added "Restricted hazardous substance device" to the ordering information.
Added drawing Output Capacitive Derating drawing.
Added M generation die step to data sheet ordering information.
Corrected note reference.
Removed /MS from datasheet header. Removed IDT's reference to fabrication.
Updated ordering information by adding Tape and Reel, updated Restricted Hazardous Substance
Device wording to Green and removed the Die Stepping Revision, the"M" designator.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
8
for Tech Support:
[email protected]
800-345-7015
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