IDT IDT7188L Cmos static ram 64k 16k x 4-bit Datasheet

IDT7188S
IDT7188L
CMOS Static RAM
64K (16K x 4-Bit)
Features
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innovative circuit design techniques, provides a cost effective approach
for memory intensive applications.
Access times as fast as 25ns are available. The IDT7188 offers a
reduced power standby mode, ISB1, which is activated when CS goes
HIGH. This capability significantly decreases power while enhancing
system reliability. The low-power version (L) version also offers a battery
backup data retention capability where the circuit typically consumes only
30µW operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a single
5V supply. The IDT7188 is packaged in a 22-pin, 300 mil ceramic DIP
providing excellent board-level packing densities.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
High-speed (equal access and cycle times)
– Military: 25/35/45/55/70/85ns (max.)
Low power consumption
Battery backup operation — 2V data retention
(L version only)
Available in high-density industry standard 22-pin, 300 mil
ceramic DIP
Produced with advanced CMOS technology
Inputs/outputs TTL-compatible
Military product compliant to MIL-STD-883, Class B
Description
The IDT7188 is a 65,536-bit high-speed static RAM organized as
16K x 4. It is fabricated using IDT’s high-performance, high-reliability
technology — CMOS. This state-of-the-art technology, combined with
Functional Block Diagram
A0
VCC
GND
65,536-BIT
MEMORY ARRAY
DECODER
A13
I/O0
I/O1
I/O2
COLUMN I/O
INPUT
DATA
CONTROL
I/O3
,
CS
WE
2989 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-2989/09
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Absolute Maximum Ratings(1)
Pin Configuration
A0
A1
A2
A3
A4
A5
A6
A7
A8
CS
GND
1
22
2
21
3
20
4
19
18
D22-1
5
6
17
7
16
8
15
9
14
10
13
11
12
V CC
A 13
A 12
A 11
A 10
A9
I/O 3
I/O 2
I/O 1
I/O 0
WE
Rating
Value
VTERM
Terminal Voltage with Respect to GND
-0.5 to +7.0
V
Operating Temperature
-55 to +125
o
C
TBIAS
Temperature Under Bias
-65 to +135
o
C
TSTG
Storage Temperature
-65 to +150
o
C
TA
Unit
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
2989 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
,
2989 drw 02
DIP
Top View
Symbol
Capacitance
(TA = +25°C, f = 1.0MHz, V CC = 0V)
Parameter(1)
Symbol
Pin Descriptions
Name
Description
A0 - A13
Address Inputs
CS
Chip Select
WE
Write Enable
I/O0 - I/O3
Data Input/Output
VCC
Power
GND
Ground
I/O Capacitance
VIN = 0V
6
pF
VOUT = 0V
6
pF
Recommended DC Operating
Conditions
Symbol
(1)
WE
I/O
Power
Standby
H
X
High-Z
Standby
Read
L
H
DOUT
Active
Write
L
L
DIN
Active
NOTE:
1. H = VIH, L = VIL, X = don't care.
CI/O
Unit
2989 tbl 04
CS
Mode
Input Capacitance
Max.
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
2989 tbl 01
Truth Table
CIN
Conditions
Parameter
VCC
Supply Voltage
GND
Ground
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
6.0
V
0.8
V
V IH
Input High Voltage
2.2
____
VIL
Input Low Voltage
-0.5(1)
____
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns,once per cycle.
2989 tbl 02
2989 tbl 05
Recommended Operating
Temperature and Supply Voltage
Grade
Military
Temperature
O
O
-55 C to +125 C
GND
Vcc
0V
5V ± 10%
2989 tbl 06
2
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
IDT7188S
Symbol
Parameter
Test Conditions
IDT7188L
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current
VCC = Max., VIN = GND to VCC
____
10
____
5
µA
|ILO|
Output Leakage Current
VCC = Max., CS = VIH, VOUT = GND to VCC
____
10
____
5
µA
VOL
Output Low Voltage
IOL = 10mA, VCC = Min.
____
0.5
____
0.5
V
IOL = 8mA, VCC = Min.
____
0.4
____
0.4
IOH = -4mA, VCC = Min.
2.4
____
2.4
____
VOH
Output High Voltage
V
2989 tbl 07
DC Electrical Characteristics(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
Symbol
ICC1
ICC2
ISB
ISB1
Power
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Unit
Operating Power
Supply Current
CS = VIL, Outputs Open
V CC = Max., f = 0(2)
S
105
105
105
105
105
105
mA
L
80
80
80
80
80
80
Dynamic Operating Current
CS = VIL, Outputs Open
V CC = Max., f = fMAX(2)
S
155
140
140
140
140
140
L
120
115
110
110
110
105
Standby Power Supply
Current (TTL Level)
CS > VIH, Outputs Open
V CC = Max., f = fMAX(2)
S
60
50
50
50
50
50
L
40
40
35
35
35
35
Full Standby Power
Supply Current (CMOS Level)
CS > VHC, VCC = Max., VIN > VHC
or VIN < VLC, f = 0(2)
S
20
20
20
20
20
20
L
1.5
1.5
1.5
1.5
1.5
1.5
Parameter
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.42
3
mA
mA
mA
2989 tbl 08
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Data Retention Characteristics
(L Version Only) (VHC = VCC - 0.2V)
Typ. (1)
VCC @
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
IILII(3)
Input Leakage Current
Max.
VCC @
Test
Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
____
2.0
____
____
____
____
V
____
10
15
600
900
µA
0
____
____
____
____
ns
tRC(2)
____
____
____
____
ns
____
____
____
2
2
µA
CS > VHC
VIN > VHC or
< VLC
2989 tbl 09
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥ 2V
t CDR
CS
VIH
VDR
tR
,
V IH
2989 drw 03
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
2989 tbl 10
5V
5V
480Ω
480Ω
DATA OUT
DATA OUT
255Ω
30pF*
255Ω
,
2989 drw 04
5pF*
2989 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tHZ , tLZ, tWZ, tOHZ and tOW )
*Includes scope and jig capacitances
4
,
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics
7188S25
7188L25
(VCC = 5.0V ± 10%)
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
25
____
35
—
45
—
55
____
70
____
85
____
ns
tAA
Address Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
tACS
Chip Select Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
tOH
Output Hold from Address Change
5
____
5
____
5
____
5
____
5
____
5
____
ns
tLZ(1)
Output Select to Output in Low-Z
5
____
5
____
5
____
5
____
5
____
5
____
ns
tHZ(1)
Chip Deselect to Output in High-Z
____
10
____
14
____
14
____
20
____
25
____
30
ns
tPU(1)
Chip Select to Power Up Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
tPD(1)
Chip Deselect to Power Down Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
Symbol
Parameter
Read Cycle
tRC
2989 tbl 11
NOTE:
1. This parameter is guaranteed by device characterization but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2)
tRC (5)
ADDRESS
tAA
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
,
2989 drw 06
Timing Waveform of Read Cycle No. 2(1,3)
tRC (5)
CS
tACS
tHZ (4)
tLZ (4)
DATAOUT
DATA VALID
tPU
VCC SUPPLY
CURRENT
HIGH IMPEDANCE
tPD
ICC
ISB
2989 drw 07
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.42
5
,
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics
7188S25
7188L25
Symbol
Parameter
(VCC = 5.0V ± 10%)
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
20
____
30
____
40
____
50
____
60
____
75
____
ns
25
____
35
____
50
____
60
____
75
____
ns
Write Cycle
tWC
Write Cycle Time
tCW
Chip Select to End-of-Write
20
____
tAW
Address Valid to End-of-Write
20
____
25
____
35
____
50
____
60
____
75
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width
20
____
25
____
35
____
50
____
60
____
75
____
ns
0
____
0
____
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
tDW
Data Valid to End-of-Write
13
____
15
____
20
____
25
____
30
____
35
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
____
7
____
10
____
15
____
25
____
30
____
40
ns
5
____
5
____
5
____
5
____
5
____
5
____
ns
tWZ(1)
Write Enable to Output in High-Z
tOW(1)
Output Active from End-of-Write
2989 tbl 12
NOTE:
1. This parameter is guaranteed by device characterization.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3)
tWC
ADDRESS
tAW
CS1, CS2
tWP
tAS
tWR
WE
tWZ (6)
DATAOUT
tOW (6)
(4)
(4)
tDW
,
tDH
DATA VALID
DATAIN
2989 drw 08
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
6
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5)
tWC
ADDRESS
tAW
CS
tAS
tCW
t WR
WE
,
tDW
DATAIN
tDH
DATA VALID
2989 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
Ordering Information
IDT
7188
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
B
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
D
300 mil Ceramic DIP (D22-1)
25
35
45
55
70
85
S
L
Speed in nanoseconds
Standard Power
Low Power
2989 drw 10
6.42
7
,
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Datasheet Document History
11/xx/99
Pg. 2, 3, 4
Pg. 8
08/09/00
02/01/01
Updated to new format
Removed commercial temperature data
Added Datasheet Document History
Not recommended for new designs
Removed "Not recommended for new designs"
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8
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