IDT IDT71V321S25TFI High-speed 3.3v 2k x 8 dual-port static ram with interrupt Datasheet

HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
IDT71V321S/L
IDT71V421S/L
Features
◆
◆
◆
◆
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT71V321/IDT71V421S
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71V321/V421L
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
Two INT flags for port-to-port communications
◆
◆
◆
◆
◆
◆
◆
MASTER IDT71V321 easily expands data bus width to 16or-more-bits using SLAVE IDT71V421
On-chip port arbitration logic (IDT71V321 only)
BUSY output flag on IDT71V321; BUSY input on IDT71V421
Fully asynchronous operation from either port
Battery backup operation—2V data retention (L only)
TTL-compatible, single 3.3V power supply
Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
BUSYL
I/O
Control
(1,2)
A10L
A0L
(1,2)
BUSYR
Address
Decoder
MEMORY
ARRAY
11
CEL
OEL
R/WL
Address
Decoder
A10R
A0R
11
ARBITRATION
and
INTERRUPT
LOGIC
CER
OER
R/WR
(2)
(2)
INTR
INTL
3026 drw 01
NOTES:
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.
2. BUSY and INT are totem-pole outputs.
AUGUST 2001
1
©2001 Integrated Device Technology, Inc.
DSC-3026/8
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port
Static RAMs with internal interrupt logic for interprocessor communications. The IDT71V321 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system applications results in full speed, error-free operation without the need for
additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (L)
versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery.
The IDT71V321/IDT71V421 devices are packaged in a 52-pin
PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP
(super thin quad flatpack).
R/WR
BUSYR
INTR
A 10R
V CC
CER
INTL
BUSYL
R/WL
CEL
87 6 5 4 3 2 1 52 51 50 49 48 47
46
45
9
44
10
43
11
42
12
IDT71V321/421J
41
13
J52-1(4)
40
14
52-Pin PLCC
39
15
Top View(5)
38
16
37
17
36
18
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
OER
A 0R
A 1R
A 2R
A 3R
A 4R
A 5R
A 6R
A 7R
A 8R
A 9R
NC
I/O7R
3026 drw 02
,
N/C
N/C
A10L
INT L
BUSYL
R/W L
CEL
VCC
VCC
CER
R/WR
BUSYR
INTR
A10R
N/C
N/C
A1L
A 2L
A 3L
A 4L
A 5L
A 6L
A 7L
A 8L
A 9L
I/O 0L
I/O 1L
I/O 2L
I/O 3L
I/O 4L
I/O 5L
I/O 6L
I/O 7L
NC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
INDEX
A 0L
OEL
A 10L
Pin Configurations(1,2,3)
IDT71V321/421PF or TF
PP64-1(4)
&
PN64-1(4)
64-Pin STQFP
64-Pin TQFP
Top View(5)
2
6.42
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O 3L
N/C
I/O 4L
I/O 5L
I/O 6L
I/O 7L
N/C
GND
GND
I/O 0R
I/O 1R
I/O 2R
I/O 3R
N/C
I/O4R
I/O5R
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
OEL
A0L
A1L
A 2L
A 3L
A 4L
A 5L
A 6L
N/C
A 7L
A 8L
A 9L
N/C
I/O 0L
I/O 1L
I/O 2L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
INDEX
OE R
A 0R
A 1R
A 2R
A 3R
A 4R
A 5R
A 6R
N/C
A 7R
A 8R
A 9R
N/C
N/C
I/O 7R
I/O 6R
3026 drw 03
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
to GND
Unit
-0.5 to +4.6
V
Grade
Ambient
Temperature
GND
Vcc
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
Commercial
Industrial
Operating
Temperature
TA
Commercial
& Industrial
Recommended Operating
Temperature and Supply Voltage(1,2)
0 to +70
°C
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
Storage
Temperature
-65 to +150
o
IOUT
DC Output
Current
50
C
C
3026 tbl 02
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Recommended DC Operating
Conditions
mA
3026 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
Symbol
Parameter
VCC
Supply Voltage
GND
Ground
VIH
VIL
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
2.0
____
Input High Voltage
(1)
Input Low Voltage
-0.3
V
(2)
VCC+0.3
____
0.8
V
V
3026 tbl 03
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + 0.3V.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
3026 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
71V321S
71V421S
Symbol
Parameter
Test Conditions
(1)
Min.
71V321L
71V421L
Max.
Min.
Max.
Unit
10
___
5
µA
|ILI|
Input Leakage Current
VCC = 3.6V,
VIN = 0V to V CC
___
|ILO|
Output Leakage Current
CE = VIH, VOUT = 0V to V CC
VCC = 3.6V
___
10
___
5
µA
VOL
Output Low Voltage
IOL = 4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
3026 tbl 05
NOTE:
1. At VCC < 2.0V input leakages are undefined.
3
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2) (VCC = 3.3V ± 0.3V)
71V321X25
71V421X25
Com'l
& Ind
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Po rts - All
CMOS Level Inputs)
Full Standby Current
(One Port - All
CMOS Level Inputs)
Test Condition
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
Version
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
mA
COM'L
S
L
55
55
130
100
55
55
125
95
55
55
115
85
IND
S
L
55
55
150
130
___
___
___
___
COM'L
S
L
15
15
35
20
15
15
35
20
15
15
35
20
IND
S
L
15
15
50
35
___
___
___
___
CE"A" = VIL and CE"B" = V IH (5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
S
L
25
25
75
55
25
25
70
50
25
25
60
40
IND
S
L
25
25
95
75
___
___
___
___
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S
L
1.0
0.2
5
3
1.0
0.2
5
3
1.0
0.2
5
3
IND
S
L
1.0
0.2
10
6
___
___
___
___
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L
S
L
25
25
70
55
25
25
65
50
25
25
55
40
IND
S
L
25
25
85
70
___
___
___
___
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
mA
mA
mA
mA
3026 tbl 06
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.).
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Data Retention Characteristics (L Version Only)
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
2.0
___
0
V
VDR
VCC for Data Retention
ICCDR
Data Retention Current
VCC = 2V, CE > VCC - 0.2V
COM'L.
___
100
1500
µA
tCDR (3)
Chip Deselect to Data
Retention Time
VIN > VCC - 0.2V or V IN < 0.2V
IND.
___
100
4000
µA
0
___
___
V
___
___
V
(3)
tR
(2)
Operation Recovery Time
tRC
3026 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
4
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
AC Test Conditions
Industrial and Commercial Temperature Ranges
Data Retention Waveform
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
DATA RETENTION MODE
VCC
3.0V
t CDR
Figures 1 and 2
3026 tbl 08
VDR ≥ 2.0V
3.0V
tR
VDR
CE
VIH
VIH
3026 drw 04
3.3V
3.3V
590Ω
DATAOUT
BUSY
INT 435Ω
590Ω
DATAOUT
435Ω
30pF
5pF
3026 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, t WZ, and tOW)
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(2)
71V321X25
71V421X25
Com 'l
& Ind
Sym bol
Param eter
71V321X35
71V421X35
Com 'l Only
71V321X55
71V421X55
Com 'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
25
____
35
____
55
____
ns
Address Access Time
____
25
____
35
____
55
ns
Chip Enable Access Time
____
25
____
35
____
55
ns
tAOE
Output Enable Access Time
____
12
____
20
____
25
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
0
____
0
____
0
____
ns
____
12
____
15
____
30
ns
0
____
0
____
0
____
ns
____
50
____
50
____
50
ns
READ CYCLE
tRC
tAA
tACE
(1,2)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time (1,2)
tPU
Chip Enable to Power Up Time (2)
tPD
Chip Disable to Power Down Time (2)
3026 tbl 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
5
6.42
,
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
3026 drw 06
tBDD (2,3)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side (3)
tACE
CE
tAOE
(4)
tHZ (2)
OE
tLZ (1)
tHZ
VALID DATA
DATAOUT
tLZ
ICC
CURRENT
ISS
(2)
(1)
tPD
tPU
50%
(4)
50%
3026 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD .
6
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
71V321X25
71V421X25
Com'l
& Ind
Symbol
Parameter
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
25
____
35
____
55
____
ns
30
____
40
____
ns
WRITE CYCLE
tWC
Write Cycle Time (5)
tEW
Chip Enable to End-of-Write
20
____
tAW
Address Valid to End-of-Write
20
____
30
____
40
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
20
____
30
____
40
____
ns
0
____
0
____
0
____
ns
12
____
20
____
20
____
ns
____
12
____
15
____
30
ns
0
____
0
____
0
____
ns
____
15
____
15
____
30
ns
0
____
0
____
0
____
ns
tWP
tWR
tDW
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
tHZ
Output High-Z Time
tDH
Data Hold Time (3)
tWZ
tOW
(1,2)
(1,2)
Write Enable to Output in High-Z
Output Active from End-of-Write
(1,2)
3026 tbl 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual t OW.
4. 'X' in part numbers indicates power rating (S or L).
5. For Master/Slave combination, tWC = t BAA + tWP , since R/W = VIL must occur after tBAA .
7
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
tHZ (7)
OE
tAW
CE
tAS(6)
tWP(2)
tHZ (7)
tWR (3)
R/W
tOW
tWZ (7)
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
3026 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
tAW
CE
tAS (6)
tEW (2)
tWR
(3)
R/W
tDW
tDH
DATA IN
3026 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= V IL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW . If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
8
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
71V321X25
71V421X25
Com'l
& Ind
Symbol
Parameter
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
20
____
20
____
30
ns
BUSY Timing (For Master IDT71V321 Only)
tBAA
BUSY Access Time from Address
____
tBDA
BUSY Disable Time from Address
____
20
____
20
____
30
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
20
____
30
ns
tBDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
30
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
20
____
ns
tWDD
tDDD
tAPS
tBDD
Write Pulse to Data Delay
(1)
____
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
(1)
(2)
(3)
BUSY Disable to Valid Data
50
____
60
____
80
ns
____
35
____
45
____
65
ns
5
____
5
____
5
____
ns
____
30
____
30
____
45
ns
0
____
0
____
0
____
ns
12
____
15
____
20
____
ns
____
50
____
60
____
80
ns
____
35
____
45
____
65
ns
BUSY Timing (For Slave IDT71V421 Only)
tWB
tWH
BUSY Input to Write (4)
(5)
Write Hold After BUSY
(1)
tWDD
Write Pulse to Data Delay
tDDD
Write Data Valid to Read Data Delay (1)
3026 tbl 11
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
t WP
R/W"A"
tDW
DATAIN "A"
tDH
VALID
tAPS
(1)
ADDR"B"
MATCH
tBDD
t BDA
tBAA
BUSY"B"
tWDD
DATAOUT"B"
VALID
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for SLAVE (71V421).
2. CE L = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
9
6.42
3026 drw 10
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(4)
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH
(1)
,
R/W"B"
(2)
3026 drw 11
NOTES:
1. tWH must be met for both BUSY input (71V421, slave) or output (71V321, master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. tWB is for the slave version (71V421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
"A" AND "B"
ADDRESSES MATCH
CE"B"
tAPS(2)
CE"A"
tBAC
tBDC
BUSY"A"
3026 drw 12
Timing Waveform of BUSY Arbritration Controlled
by Address Match Timing(1)
tRC
ADDR"A"
OR tWC
ADDRESSES MATCH
tAPS
ADDRESSES DO NOT MATCH
(2)
ADDR"B"
tBAA
tBDA
BUSY"B"
3026 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).
10
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
71V 321X25
71V 421X25
Com 'l
& Ind
Sym bol
Param eter
71V 321X35
71V 421X35
Com 'l Only
71V 321X55
71V 421X55
Com 'l Only
M in.
M ax.
M in.
M ax.
M in.
M ax.
Unit
INTERRUPT TIM ING
tAS
A d d re s s S et-up Tim e
0
____
0
____
0
____
ns
tWR
W rite Rec o v e ry Tim e
0
____
0
____
0
____
ns
tINS
Inte rrup t S e t Tim e
____
25
____
25
____
45
ns
tINR
Inte rrup t Re se t Tim e
____
25
____
25
____
45
ns
3026 tbl 12
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Interrupt Mode(1)
SET INT
tWC
ADDR"A"
INTERRUPT ADDRESS
(2)
tWR(4)
tAS (3)
R/W"A"
tINS (3)
INT"B"
3026 drw 14
CLEAR INT
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
tAS(3)
OE"B"
tINR(3)
INT"A"
3026 drw 15
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
11
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables
Table I. Non-Contention
Read/Write Control(4)
Left or Right Port(1)
R/W
CE
OE
D0-7
X
H
X
Z
Port Deselected and in PowerDown Mode. ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down Mode ISB1
or ISB3
L
L
X
DATAIN
H
L
L
DATA OUT
H
L
H
Z
Function
Data on Port Written Into Memory (2)
Data in Memory Output on Port(3)
High-impedance Outputs
3026 tbl 13
NOTES:
1. A0L – A 10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
Table II. Interrupt Flag(1,4)
Left Port
CEL
R/WL
L
OEL
L
X
X
7FF
X
X
X
L
INTL
A10L-A0L
X
X
X
Right Port
L
X
CER
R/WR
X
X
X
A10R-A0R
INTR
X
L(2)
(3)
Function
Set Right INTR Flag
Reset Right INTR Flag
X
X
X
L
L
7FF
H
X
L(3)
L
L
X
7FE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
7FE
H
3026 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Table III — Address BUSY Arbitration
Inputs
OER
Outputs
CEL
CER
AOL-A10L
AOR -A10R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
3026 tbl 15
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71V321 (master). Both are inputs
for IDT71V421 (slave). BUSYX outputs on the IDT71V321 are totem-pole. On
slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. 'H' if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSY R
= LOW will result. BUSYL and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
12
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
The IDT7V1321/IDT71V421 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT71V321/IDT71V421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CER = R/WR = VIL per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag (INTR) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
being expanded in depth, then the BUSY indication for the resulting array
requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an SRAM array in width while using BUSY logic, one
master part is used to decide which side of the SRAM array will receive
a BUSY indication. Any number of slaves to be addressed in the same
address range as the master, use the BUSY signal as a write inhibit signal.
Thus on the IDT71V321/IDT71V421 SRAMs the BUSY pin is an output
if the part is Master (IDT71V321), and the BUSY pin is an input if the part
is a Slave (IDT71V421) as shown in Figure 3.
MASTER
Dual Port
RAM
BUSYL
MASTER
Dual Port
RAM
BUSYL
BUSYL
CE
BUSYR
CE
BUSYR
SLAVE
Dual Port
RAM
BUSYL
SLAVE
Dual Port
RAM
BUSYL
CE
BUSYR
DECODER
Functional Description
CE
BUSYR
BUSYR
3026 drw 16
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation.
The BUSY outputs on the IDT71V321 RAM master are totem-pole type
outputs and do not require pull-up resistors to operate. If these RAMs are
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
13
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
A
Device Type Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
J
PF
TF
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
25
35
55
Commercial & Industrial
Commercial Only
Commercial Only
L
S
Low Power
Standard Power
71V321
16K (2K x 8-Bit) MASTER 3.3V
Dual-Port RAM w/ Interrupt
16K (2K x 8-Bit) SLAVE 3.3V
Dual-Port RAM w/ Interrupt
71V421
NOTE:
1. Contact your sales office Industrial temperature range is available for selected speeds, packages and powers.
Speed in nanoseconds
3026 drw 17
Datasheet Document History
03/24/99:
06/15/99:
10/15/99:
10/21/99:
11/12/99:
01/12/01:
08/22/01:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 Added additional notes to pin configurations
Changed drawing format
Page 12 Changed open drain to totem-pole in Table III, note 1
Page 13 Deleted 'does not' in copy from Busy Logic
Replaced IDT logo
Pages 1 & 2 Moved full "Description" to page 2 and adjusted page layouts
Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
Pages 4, 5, 7, 9 & 11 Industrial temp range offering removed from DC & AC Electrical Characteristics for 35 and 55ns
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14
6.42
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