IDT IDT7206L50J Cmos asynchronous fifo 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 Datasheet

CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9,
8192 x 9 and 16384 x 9
IDT7203
IDT7204
IDT7205
IDT7206
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
The IDT7203/7204/7205/7206 are dual-port memory buffers with internal pointers that load and empty data on a firstin/first-out basis. The device uses Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of
the Write ( ) and Read ( ) pins.
The devices 9-bit width provides a bit for a control or parity
at the user’s option. It also features a Retransmit ( ) capability that allows the read pointer to be reset to its initial position
when
is pulsed LOW. A Half-Full Flag is available in the
single device and width expansion modes.
The IDT7203/7204/7205/7206 are fabricated using IDT’s
high-speed CMOS technology. They are designed for applications requiring asynchronous and simultaneous read/writes
in multiprocessing, rate buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
•
•
•
•
•
•
•
•
•
First-In/First-Out Dual-Port memory
2048 x 9 organization (IDT7203)
4096 x 9 organization (IDT7204)
8192 x 9 organization (IDT7205)
16384 x 9 organization (IDT7206)
High-speed: 12ns access time
Low power consumption
— Active: 770mW (max.)
— Power-down: 44mW (max.)
Asynchronous and simultaneous read and write
Fully expandable in both word depth and width
Pin and functionally compatible with IDT720X family
Status Flags: Empty, Half-Full, Full
Retransmit capability
High-performance CMOS technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing for #5962-88669 (IDT7203),
5962-89567 (IDT7203), and 5962-89568 (IDT7204) are
listed on this function
Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
W
R
RT
RT
.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D 0 –D 8 )
W
WRITE
CONTROL
WRITE
POINTER
RAM ARRAY
2048 x 9
4096 x 9
8192 x 9
16384 x 9
READ
POINTER
THREESTATE
BUFFERS
R
READ
CONTROL
FLAG
LOGIC
RESET
LOGIC
/
FL RT
EF
FF
EXPANSION
LOGIC
XI
RS
DATA OUTPUTS
(Q 0 –Q 8 )
/
XO HF
2661 drw 01
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.04
DECEMBER 1996
DSC-2661/9
1
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FF
Q0
Q1
Q2
Q3
Q8
GND
P28-1
P28-2
D28-1
D28-3
SO28-3
4
3
2
32
31
30
INDEX
Vcc
D4
D5
D6
D7
D2
D1
D0
FL/RT
XI
RS
FF
EF
Q0
Q1
NC
Q2
XO/HF
Q7
Q6
Q5
Q4
R
5
6
7
8
9
10
11
12
13
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
J32-1
&
L32-1
29
28
27
26
25
24
23
22
21
D6
D7
NC
FL /RT
RS
EF
/
XO HF
Q7
Q6
14
15
16
17
18
19
20
XI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Q3
Q8
GND
NC
R
Q4
Q5
W
D8
D3
D2
D1
D0
D3
D8
W
NC
Vcc
D4
D5
PIN CONFIGURATIONS
2661 drw 02b
2661 drw 02a
PLCC/LCC
TOP VIEW
DIP
TOP VIEW
NOTES:
1. The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/
7205.
2. The small outline package SO28-3 is only available for the 7204.
3. Consult factory for CERPACK pinout.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Unit
V
Symbol
Commercial
Military
Terminal
Voltage with
Respect to
GND
–0.5 to + 7.0
–0.5 to +7.0
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to + 125
–65 to +155
°C
VTERM
IOUT
Rating
RECOMMENDED DC OPERATING
CONDITIONS
DC Output
Current
50
50
Min.
Typ.
Max.
Unit
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
VCCC
Commercial Supply
Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH(1)
Input High Voltage
Commercial
2.0
—
—
V
VIH(1)
Input High Voltage
Military
2.2
—
—
V
VIL(1)
Input Low Voltage
Commercial and
Military
—
—
0.8
V
mA
NOTE:
2661 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Parameter
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
5.04
2661 tbl 02
2
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
IDT7203/7204
Commercial
tA = 12, 15, 20, 25, 35, 50 ns
Symbol
Parameter
IDT7203/7204
Military(1)
tA = 20, 30, 40, 50, 65, 80, 120 ns
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
ILI(2)
Input Leakage Current (Any Input)
–1
—
1
–1
—
1
µA
ILO(3)
Output Leakage Current
–10
—
10
–10
—
10
µA
VOH
Output Logic “1” Voltage IOH = –2mA
2.4
—
—
2.4
—
—
V
VOL
Output Logic “0” Voltage IOL = 8mA
—
—
0.4
—
—
0.4
V
ICC1(4)
Active Power Supply Current
—
—
120
—
—
150
mA
ICC2(4)
Standby Current (R=W=RS=FL/RT=VIH)
—
—
12
—
—
25
mA
ICC3(L)(4)
Power Down Current (All Input = VCC - 0.2V)
—
—
2
—
—
4
mA
(4)
Power Down Current (All Input = VCC - 0.2V)
—
—
8
—
—
12
mA
ICC3(S)
(5)
(5)
NOTES:
1. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. ICC measurements are made with outputs open (only capacitive loading).
5. Tested at f = 20MHz.
2661 tbl 03
DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
IDT7205/7206
Commercial
tA = 15, 20, 25, 35, 50 ns
Symbol
Parameter
IDT7205/7206
Military
tA = 20, 30, 50 ns
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Input Leakage Current (Any Input)
–1
—
1
–1
—
1
µA
ILO(2)
Output Leakage Current
–10
—
10
–10
—
10
µA
VOH
Output Logic “1” Voltage IOH = –2mA
2.4
—
—
2.4
—
—
V
VOL
Output Logic “0” Voltage IOL = 8mA
—
—
0.4
—
—
0.4
V
ICC1(3)
Active Power Supply Current
—
—
120(4)
—
—
150(4)
mA
Standby Current (R=W=RS=FL/RT=VIH)
—
—
12
—
—
25
mA
Power Down Current (All Input = VCC - 0.2V)
—
—
8
—
—
12
ILI
(1)
ICC2(3)
ICC3(L)
(3)
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
5.04
mA
2661 tbl 04
3
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
7203S/L12
7204S/L12
Symbol
Parameters
7203S/L15
7204S/L15
7205L15
7206L15
Com'l & Mil.
Com'l
7203S/L20
7204S/L20
7205L20
7206L20
7203S/L25
7204S/L25
7205L25
7206L25
Min. Max. Min. Max. Min.
Max.
Military
Com'l
7203S/L30 7203S/L35
7204S/L30 7204S/L35
7205L30
7205L35
7206L30
7206L35
Min. Max. Min. Max. Min. Max. Unit
fS
Shift Frequency
—
50
—
40
—
33.3
—
28.5
—
25
—
tRC
Read Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
tA
Access Time
—
12
—
15
—
20
—
25
—
30
—
35
ns
tRR
Read Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
(2)
22.2 MHz
tRPW
Read Pulse Width
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRLZ
Read LOW to Data Bus LOW(3)
3
—
5
—
5
—
5
—
5
—
5
—
ns
3
—
5
—
5
—
5
—
5
—
10
—
ns
5
—
5
—
5
—
5
—
5
—
5
—
ns
tWLZ
Write HIGH to Data Bus Low-Z
tDV
Data Valid from Read HIGH
(3, 4)
(3)
tRHZ
Read HIGH to Data Bus High-Z
—
12
—
15
—
15
—
18
—
20
—
20
ns
tWC
Write Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
(2)
tWPW
Write Pulse Width
12
—
15
—
20
—
25
—
30
—
35
—
ns
tWR
Write Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tDS
Data Set-up Time
9
—
11
—
12
—
15
—
18
—
18
—
ns
tDH
Data Hold Time
0
—
0
—
0
—
0
—
0
—
0
—
ns
tRSC
Reset Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
tRS
Reset Pulse Width(2)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRSS
Reset Set-up Time(3)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRTR
Reset Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tRTC
Retransmit Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
tRT
Retransmit Pulse Width(2)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRTS
Retransmit Set-up Time(3)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRSR
Retransmit Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tEFL
Reset to EF LOW
—
12
—
25
—
30
—
35
—
40
—
45
ns
—
17
—
25
—
30
—
35
—
40
—
45
ns
tHFH, tFFH Reset to HF and FF HIGH
tRTF
Retransmit LOW to Flags Valid
—
20
—
25
—
30
—
35
—
40
—
45
ns
tREF
Read LOW to EF LOW
—
12
—
15
—
20
—
25
—
30
—
30
ns
tRFF
Read HIGH to FF HIGH
—
14
—
15
—
20
—
25
—
30
—
30
ns
tRPE
Read Pulse Width after EF HIGH
12
—
15
—
20
—
25
—
30
—
35
—
ns
tWEF
Write HIGH to EF HIGH
—
12
—
15
—
20
—
25
—
30
—
30
ns
tWFF
Write LOW to FF LOW
—
14
—
15
—
20
—
25
—
30
—
30
ns
tWHF
Write LOW to HF Flag LOW
—
17
—
25
—
30
—
35
—
40
—
45
ns
tRHF
Read HIGH to HF Flag HIGH
—
17
—
25
—
30
—
35
—
40
—
45
ns
tWPF
Write Pulse Width after FF HIGH
12
—
15
—
20
—
25
—
30
—
35
—
ns
tXOL
Read/Write LOW to XO LOW
—
12
—
15
—
20
—
25
—
30
—
35
ns
tXOH
Read/Write HIGH to XO HIGH
—
12
—
15
—
20
—
25
—
30
—
35
ns
tXI
XI
12
—
15
—
20
—
25
—
30
—
35
—
ns
tXIR
XI
Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tXIS
XI
Set-up Time
8
—
10
—
10
—
10
—
10
—
15
—
ns
Pulse Width(2)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
2661 tbl 05
5.04
4
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Symbol
Parameters
Military
Com'l & Mil.
7203S/L40
7204S/L40
7203S/L50
7204S/L50
7205L50
7206L50
Military(2)
7203S/L65
7204S/L65
Max. Min.
7203S/L120
7204S/L120
Min.
Max.
Min.
Max.
Unit
fS
Shift Frequency
—
20
—
15
—
12.5
—
10
—
7
MHz
tRC
Read Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
tA
Access Time
—
40
—
50
—
65
—
80
—
120
ns
tRR
Read Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
(3)
Max. Min.
7203S/L80
7204S/L80
Max. Min.
tRPW
Read Pulse Width
40
—
50
—
65
—
80
—
120
—
ns
tRLZ
Read LOW to Data Bus LOW(4)
5
—
10
—
10
—
10
—
10
—
ns
10
—
15
—
15
—
20
—
20
—
ns
(4, 5)
tWLZ
Write HIGH to Data Bus Low-Z
tDV
Data Valid from Read HIGH
5
—
5
—
5
—
5
—
5
—
ns
tRHZ
Read HIGH to Data Bus High-Z(4)
—
25
—
30
—
30
—
30
—
35
ns
tWC
Write Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
tWPW
Write Pulse Width(3)
40
—
50
—
65
—
80
—
120
—
ns
tWR
Write Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
tDS
Data Set-up Time
20
—
30
—
30
—
40
—
40
—
ns
tDH
Data Hold Time
0
—
5
—
10
—
10
—
10
—
ns
tRSC
Reset Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
tRS
Reset Pulse Width(3)
40
—
50
—
65
—
80
—
120
—
ns
(4)
40
—
50
—
65
—
80
—
120
—
ns
tRSS
Reset Set-up Time
tRSR
Reset Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
tRTC
Retransmit Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
tRT
(3)
Retransmit Pulse Width
40
—
50
—
65
—
80
—
120
—
ns
tRTS
Retransmit Set-up Time(4)
40
—
50
—
65
—
80
—
120
—
ns
tRSR
Retransmit Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
tEFL
Reset to EF LOW
—
50
—
65
—
80
—
100
—
140
ns
tHFH, tFFH
Reset to HF and FF HIGH
—
50
—
65
—
80
—
100
—
140
ns
tRTF
Retransmit LOW to Flags Valid
—
50
—
65
—
80
—
100
—
140
ns
tREF
Read LOW to EF Flag LOW
—
35
—
45
—
60
—
60
—
60
ns
tRFF
Read HIGH to FF HIGH
—
35
—
45
—
60
—
60
—
60
ns
tRPE
Read Pulse Width after EF HIGH
40
—
50
—
65
—
80
—
120
—
ns
tWEF
Write HIGH to EF HIGH
—
35
—
45
—
60
—
60
—
60
ns
tWFF
Write LOW to FF LOW
—
35
—
45
—
60
—
60
—
60
ns
tWHF
Write LOW to HF LOW
—
50
—
65
—
80
—
100
—
140
ns
tRHF
Read HIGH to HF HIGH
—
50
—
65
—
80
—
100
—
140
ns
tWPF
Write Pulse Width after FF HIGH
40
—
50
—
65
—
80
—
120
—
ns
tXOL
Read/Write LOW to XO LOW
—
40
—
50
—
65
—
80
—
120
ns
tXOH
Read/Write HIGH to XO HIGH
tXI
XI
tXIR
tXIS
—
40
—
50
—
65
—
80
—
120
ns
Pulse Width(3)
40
—
50
—
65
—
80
—
120
—
ns
XI
Recovery Time
10
—
10
—
10
—
10
—
10
—
ns
XI
Set-up Time
15
—
15
—
15
—
15
—
15
—
ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
2661 tbl 06
5.04
5
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
1.1KΩ
D.U.T.
2661 tbl 07
680Ω
30pF*
CAPACITANCE(1) (TA = +25°C, f = 1.0 MHz)
Symbol
Parameter
Condition
Max.
Unit
Input Capacitance
VIN = 0V
10
pF
Output Capacitance
VOUT = 0V
10
pF
CIN(1)
(1,2)
COUT
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
2661 drw 03
OR EQUIVALENT CIRCUIT
Figure 1. Output Load
2661 tbl 08
*Includes jig and scope capacitances.
SIGNAL DESCRIPTIONS
Inputs:
DATA IN (D0–D8) — Data inputs for 9-bit wide data.
Controls:
RESET (RS) — Reset is accomplished whenever the Reset
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take place.
Both the Read Enable (R) and Write Enable (W) inputs must
be in the HIGH state during the window shown in Figure 2
(i.e. tRSS before the rising edge of RS) and should not
change until tRSR after the rising edge of RS.
WRITE ENABLE (W) — A write cycle is initiated on the falling
edge of this input if the Full Flag (FF) is not set. Data set-up and
hold times must be adhered-to, with respect to the rising edge
of the Write Enable (W). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to LOW,
and will remain set until the difference between the write pointer
and read pointer is less-than or equal to one-half of the total
memory of the device. The Half-Full Flag (HF) is reset by the
rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW on
the falling edge of the last write signal, which inhibits further write
operations. Upon the completion of a valid read operation, the
Full Flag (FF) will go HIGH after tRFF, allowing a new valid write
to begin. When the FIFO is full, the internal write pointer is
blocked from W, so external changes in W will not affect the FIFO
when it is full.
READ ENABLE (R) — A read cycle is initiated on the falling
edge of the Read Enable (R), provided the Empty Flag (EF) is not
set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R)
goes HIGH, the Data Outputs (Q0 through Q8) will return to a
high-impedance condition until the next Read operation. When
all the data has been read from the FIFO, the Empty Flag (EF)
will go LOW, allowing the “final” read cycle but inhibiting further
read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tWEF and a valid
Read can then begin. When the FIFO is empty, the internal read
pointer is blocked from R so external changes will not affect the
FIFO when it is empty.
FIRST LOAD/RETRANSMIT (FL/RT) — This is a dualpurpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first device loaded (see
Operating Modes). The Single Device Mode is initiated by
grounding the Expansion In (XI).
The IDT7203/7204/7205/7206 can be made to retransmit
data when the Retransmit Enable Control (RT) input is pulsed
LOW. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. The status
of the Flags will change depending on the relative locations of
the read and write pointers. Read Enable (R) and Write Enable
(W) must be in the HIGH state during retransmit. This feature is
useful when less than 2048/4096/8192/16384 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode.
EXPANSION IN (XI) — This input is a dual-purpose pin.
Expansion In (XI) is grounded to indicate an operation in the
single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or
Daisy-Chain Mode.
5.04
6
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Outputs:
FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibiting
further write operations, when the device is full. If the read
pointer is not moved after Reset (RS), the Full Flag (FF) will go
LOW after 2048/4096/8192/16384 writes.
EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW,
inhibiting further read operations, when the read pointer is equal
to the write pointer, indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (XO/HF) — This is a
dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a halffull memory.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to LOW
and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
memory of the device. The Half-Full Flag (HF) is then reset by
the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an XO pulse
when the Write pointer reaches the last location of memory, and
an additional XO pulse when the Read pointer reaches the last
location of memory.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9bit wide data. These outputs are in a high-impedance condition
whenever Read (R) is in a HIGH state.
t RSC
t RS
RS
t RSS
t RSR
W
t RSS
R
t EFL
EF
t HFH , t FFH
,
HF FF
2661 drw 04
NOTE:
1. W and R = VIH around the rising edge of RS.
Figure 2. Reset
t RC
t RPW
t RR
tA
tA
R
t DV
t RLZ
DATA OUT VALID
Q 0 –Q 8
t RHZ
DATA OUT VALID
t WC
t WPW
t WR
W
t DS
D 0 –D 8
t DH
DATA IN VALID
DATA IN VALID
2661 drw 05
Figure 3. Asynchronous Write and Read Operation
5.04
7
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IGNORED
WRITE
LAST WRITE
FIRST READ
R
W
t WFF
t RFF
FF
2661 drw 06
Figure 4. Full FlagTiming From Last Write to First Read
IGNORED
READ
LAST READ
FIRST WRITE
W
R
t REF
t WEF
EF
tA
DATA OUT
VALID
2661 drw 07
Figure 5. Empty Flag Timing From Last Read to First Write
t RTC
t RT
RT
t RTS
t RTR
,
W R
RTF
,
,
FLAG VALID
HF EF FF
2661 drw 08
NOTE:
1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
5.04
8
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
t WEF
EF
t RPE
R
2661 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
t RFF
FF
t WPF
W
2661 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
W
t RHF
R
t WHF
HALF-FULL OR LESS
HF
MORE THAN HALF-FULL
HALF-FULL OR LESS
2661 drw 11
Figure 9. Half-Full Flag Timing
W
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
R
t XOL
t XOH
t XOL
t XOH
XO
2661 drw 12
Figure 10. Expansion Out
5.04
9
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t XI
t XIR
XI
t XIS
W
WRITE TO
FIRST PHYSICAL
LOCATION
t XIS
READ FROM
FIRST PHYSICAL
LOCATION
R
2661 drw 11
Figure 11. Expansion In
OPERATING MODES:
USAGE MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e. FF is monitored on the device
where W is used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and
Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT7203/7204/7205/7206 may be used when the
application requirements are for 2048/4096/8192/16384 words
or less. The IDT7203/7204/7205/7206 is in a Single Device
Configuration when the Expansion In (XI) control input is
grounded (see Figure 12).
Depth Expansion
The IDT7203/7204/7205/7206 can easily be adapted to
applications when the requirements are for greater than 2048/
4096/8192/16384 words. Figure 14 demonstrates Depth Expansion using three IDT7203/7204/7205/7206s. Any depth
can be attained by adding additional IDT7203/7204/7205/
7206s. The IDT7203/7204/7205/7206 operates in the Depth
Expansion mode when the following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EFs and ORing of all FFs (i.e. all must be set to generate the
correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: Cascading
FIFOs or FIFO Modules.
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7203/7204/7205/7206s. Any word width can be attained
by adding additional IDT7203/7204/7205/7206s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7203/7204/7205/7206s as
shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus
until the R line is raised from LOW-to-HIGH, after which the
bus would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being LOW causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.04
10
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HF)
(HALF–FULL FLAG)
WRITE (W)
READ (R)
9
IDT
7203/
7204/
7205/
7206
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
9
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
2661 drw 14
Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode
HF
18
HF
9
9
DATA IN (D)
WRITE (W)
FULL FLAG (FF)
RESET (RS)
IDT
7203/
7204/
7205/
7206
READ (R)
IDT
7203/
7204/
7205/
7206
9
EMPTY FLAG (EF)
RETRANSMIT (RT)
9
XI
XI
18
DATA OUT (Q)
2661 drw 15
NOTE:
1. Flag detection is accomplished by monitoring the FF,
Do not connect any output signals together.
EF
and HF signals on either (any) device used in the width expansion configuration.
Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode
5.04
11
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I – RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs
Mode
Reset
Internal Status
Outputs
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
HF
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment (1)
Increment (1)
X
X
X
NOTE:
1. Pointer will Increment if flag is HIGH.
2661 tbl 09
TABLE II – RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
Mode
Internal Status
Outputs
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset First Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
Read/Write
1
X
(1)
X
X
X
X
2661 tbl 10
NOTES:
1. XI is connected to XO of previous device. See Figure 14.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
XO
W
FF
D
9
9
IDT
7203/
7204/
7205/
7206
R
EF
9
FL
Q
VCC
XI
XO
FF
FULL
9
IDT
7203/
7204/
7205/
7206
EF
EMPTY
FL
XI
XO
FF
9
RS
IDT
7203/
7204/
7205/
7206
EF
FL
XI
2661 drw 16
Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion)
5.04
12
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Q 0 –Q 8
Q 9 –Q 17
Q 0 –Q 8
Q 9 –Q 17
Q (N-8) -Q N
•••
,
IDT7203/
IDT7204/
IDT7205/
IDT7206
DEPTH
EXPANSION
BLOCK
IDT7203/
IDT7204/
IDT7205/
IDT7206
DEPTH
EXPANSION
BLOCK
,
R W RS
D 0 -D 8
Q (N-8) -Q N
•••
IDT7203/
IDT7204/
IDT7205/
IDT7206
DEPTH
EXPANSION
BLOCK
D 9 -D 17
D 0 –D N
D (N-8) -D N
•••
D 9 -D N
D 18 -D N
D (N-8) -D N
2661 drw 17
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
WA
FFA
RB
IDT
7203/
IDT
7204/
7201A
7205/
7206
DA 0-8
EF B
HF B
Q B 0-8
SYSTEM A
SYSTEM B
Q A 0-8
RA
HF A
EF A
D B 0-8
IDT
7203/
7204/
7205/
7206
WB
FF B
2661 drw 18
Figure 16. Bidirectional FIFO Operation
DATA IN
W
t RPE
R
EF
t WEF
t REF
tA
t WLZ
DATA OUT
DATA VALID OUT
2661 drw 19
Figure 17. Read Data Flow-Through Mode
5.04
13
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
R
t
WPF
W
t RFF
FF
t WFF
DATA
DATA IN
t
t DH
IN
VALID
t DS
A
DATA OUT
DATA
OUT
VALID
2661 drw 20
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
IDT
XXXX
X
DeviceType Power
XX
X
X
Speed
Package
Process/
Temperature
Range
5.04
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
TP
D
TD
J
L
SO
Plastic DIP
Plastic THINDIP
Ceramic DIP
Ceramic THINDIP (all except 7206)
Plastic Leaded Chip Carrier
Leadless Chip Carrier (Military only)
Small Outline IC (7204 only)
12
15
20
25
30
35
40
50
65
80
120
Commercial 7203/04 Only
Commercial Only
S
L
Standard Power (7203/7204 only)
Low Power
7203
7204
7205
7206
2048 x 9 FIFO
4096 x 9 FIFO
8192 x 9 FIFO
16384 x 9 FIFO
Commercial Only
Military Only
Commercial Only
Military 7203/04 Only
Access Time (tA)
Speed in ns
Military 7203/04DB Only
2661 drw 21
14
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