IDT IDT72131L35P Cmos parallel-to-serial fifo 2048 x 9 4096 x 9 Datasheet

IDT72131
IDT72141
CMOS PARALLEL-TO-SERIAL FIFO
2048 X 9
4096 X 9
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 7-9, 16-18, 32-36
bit using Flexishift serial output without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-Port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low power CMOS
technology
• Available in 28-pin plastic DIP
• Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
The IDT72131/72141 are high-speed, low power parallelto-serial FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IDT72131/72141 can be configured with the IDTs serial-to-parallel FIFOs (IDT72132/72142)
for bidirectional serial data buffering.
The FIFO has a 9-bit parallel input port and a serial output
port. Wider and deeper parallel-to-serial data buffers can be
built using multiple IDT72131/72141 chips. IDTs unique
Flexishift serial expansion logic (SOX, NR) makes width
expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IDT72131/141 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The almost-full (7/8), half-full, and almost empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72131/72141 is fabricated using IDTs high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
D 0 -D 8
W
1
D4
2
27
AEF
/HF
D5
D3
3
26
D6
FF
D2
4
25
D7
D1
5
24
D8
EF
FLAG
LOGIC
W
RS
FL/RT
RAM ARRAY
2048 x 9
4096 x 9
WRITE
POINTER
NEXT READ
POINTER
NR
SOCP
XI
EXPANSION
LOGIC
SOX
SO
SERIAL OUTPUT
CIRCUITRY
XO/
Q 4 Q 6 Q7 Q 8
Vcc
D0
6
XI
7
SOX
8
21
SOCP
9
20
FL/RT
RS
EF
XO/HF
10
19
GND
11
18
Q8
SO
RESET LOGIC
28
AEF
FF
P28-1
&
C28-3
23
22
12
17
Q7
Q4
13
16
Q6
GND
14
15
NR
2751 drw 01
DIP
TOP VIEW
2751 drw 02a
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
DECEMBER 1996
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.34
DSC-2751/6
1
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
D0–D8
Inputs
I
RS
Reset
I
W
Write
I
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
NR
Serial Output
Clock
Next Read
I
FL/RT
To program the Serial Out data word width , connect NR with one of the Data Set pins (Q4, Q6,
Q7 and Q8). For example, NR - Q7 programs for a 8-bit Serial Out word width.
First Load/
I
SOCP
Data inputs for 9-bit wide data.
When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM
array. HF and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE
after power-up. W must be HIGH and SOCP must be LOW during RS cycle.
A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data setup and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored
in the RAM array sequentially and independently of any ongoing read operation.
This is a dual purpose input. In the single device configuration (XI grounded), activating retransmit
(FL/RT-LOW) will set the internal READ pointer to the first location. There is no effect on the
WRITE pointer. W must be high and SOCP must be low before setting FL/RT LOW. Retransmit
is not compatible with depth expansion. In the depth expansion configuration, FL/RT grounded
indicates the first activated device.
Retransmit
XI
Expansion In
I
In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion,
XI is connected to XO (expansion out) of the previous device.
SOX
Serial Output
I
In the Serial Output Expansion mode, the SOX pin of the least significant device is tied HIGH.
The SOX pin of all other devices is connected to the Q8 pin of the previous device. Data is then
clocked out least significant bit first. For single device operation, SOX is tied HIGH.
Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first.
In the Serial Width Expansion mode the SO pins are tied together and each SO pin is tristated
at the end of the byte.
Expansion
SO
Serial Output
O
FF
Full Flag
O
When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is
HIGH, the device is not full.
EF
Empty Flag
O
When EF goes LOW, the device is empty and further READ operations are inhibited. When EF
is HIGH, the device is not empty. See the description on page 6 for more details.
Almost-Empty/
Almost-Full Flag
O
When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
Expansion Out/
Half-Full Flag
O
Data Set
O
AEF
XO/HF
Q4, Q6,
Q7 and
Q8
This is a dual-purpose output. In the single device configuration (XI grounded), the device is more
than half full when HF is LOW. In the depth expansion configuration (XO connected to XI of the
next device), a pulse is sent from XO to XI when the last location in the RAM array is filled.
The appropriate Data Set pin (Q4, Q6, Q7 and Q8) is connected to NR to program the Serial Out
data word width. For example: Q6 - NR programs a 7-bit word width, Q8 - NR programs a 9-bit
word width, etc.
VCC
Power Supply
Single Power Supply of 5V.
GND
Ground
Single ground at 0V.
2751 tbl 01
STATUS FLAGS
Number of Words in FIFO
IDT72131
IDT72141
FF
AEF
HF
EF
0
0
H
L
H
L
1-255
1-511
H
L
H
H
256-1024
512-2048
H
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L
H
2048
4096
L
L
L
H
2751 tbl 02
5.34
2
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
°C
TBIAS
Temperature
Under Bias
–55 to +125
°C
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output
Current
50
mA
Symbol
Parameter
Min.
Typ.
Max. Unit
4.5
5.0
5.5
V
0
0
0
V
VCC
Commercial Supply
Voltage
GND
Supply Voltage
VIH
Input High Voltage
Commercial
2.0
—
—
V
VIL(1)
Input Low Voltage
—
—
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2751 tbl 04
NOTE:
2751 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
10
pF
COUT
Output Capacitance
VOUT = 0V
12
pF
NOTE:
1. This parameter is sampled and not 100% tested.
2751 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C
IDT72131/IDT72141
Commercial
Symbol
IIL
(1)
Parameter
Input Leakage Current
(Any Input)
Min.
Typ.
Max.
Unit
–1
—
1
µA
IOL(2)
Output Leakage Current
–10
—
10
µA
VOH
Output Logic "1" Voltage,
IOUT = -8mA
2.4
—
—
V
VOL
Output Logic "0" Voltage
IOUT = 16mA
—
—
0.4
V
Power Supply Current
—
90
140
mA
ICC2
Average Standby Current
(W = RS = FL/RT = VIH)
(SOCP = VIL)
—
8
12
mA
ICC3(L)(3,4)
Power Down Current
—
—
2
mA
ICC1(3)
(3)
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. SOCP ≤ VIL, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open.
4. RS = FL/RT = W = VCC -0.2V; SOCP ≤ 0.2V; all other inputs ≥ VCC -0.2V or ≤ 0.2V.
5.34
2751 tbl 06
3
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
Commercial
Symbol
Parameter
IDT72131L35
IDT72141L35
Min.
Max.
IDT72131L50
IDT72141L50
Min.
Max.
Unit
tS
Parallel Shift Frequency
—
22.2
—
15
MHz
tSOCP
Serial-Out Shift Frequency
—
50
—
40
MHz
PARALLEL INPUT TIMINGS
tDS
Data Set-up Time
18
—
30
—
ns
tDH
Data Hold Time
0
—
5
—
ns
tWC
Write Cycle Time
45
—
65
—
ns
tWPW
Write Pulse Width
35
—
50
—
ns
tWR
Write Recovery Time
10
—
15
—
ns
tWEF
Write High to EF HIGH
tWFF
tWF
tWPF
—
30
—
45
ns
Write Low to FF LOW
—
30
—
45
ns
—
45
—
65
ns
Write Pulse Width After FF HIGH
35
—
50
—
ns
Write Low to Transitioning HF, AEF
SERIAL OUTPUT TIMINGS
tSOHZ
SOCP Rising Edge to SO at High-Z(1)
5
16
5
26
ns
tSOLZ
SOCP Rising Edge to SO at Low-Z(1)
5
22
5
22
ns
tSOPD
SOCP Rising Edge to Valid Data on SO
—
18
—
18
ns
tSOX
SOX Set-up Time to SOCP Rising Edge
5
—
5
—
ns
tSOCW
Serial In Clock Width HIGH/LOW
8
—
10
—
ns
tSOCEF
SOCP Rising Edge (Bit 0 - Last Word) to EF LOW
tSOCFF
tSOCF
tREFSO
SOCP Rising Edge to FF HIGH
SOCP Rising Edge to HF, AEF, HIGH
Recovery Time SOCP After EF HIGH
—
20
—
25
ns
—
30
—
40
ns
—
30
—
40
ns
35
—
50
—
ns
RESET TIMINGS
tRSC
Reset Cycle Time
45
—
65
—
ns
tRS
Reset Pulse Width
35
—
50
—
ns
tRSS
Reset Set-up Time
35
—
50
—
ns
tRSR
Reset Recovery Time
10
—
15
—
ns
tRSF1
Reset to EF and AEF LOW
—
45
—
65
ns
tRSF2
Reset to HF and FF HIGH
—
45
—
65
ns
tRSQL
Reset to Q LOW
20
—
35
—
ns
tRSQH
Reset to Q HIGH
20
—
35
—
ns
RETRANSMIT TIMINGS
tRTC
Retransmit Cycle Time
45
—
65
—
ns
tRT
Retransmit Pulse Width
35
—
50
—
ns
tRTS
Retransmit Set-up Time
35
—
50
—
ns
tRTR
Retransmit Recovery Time
10
—
15
—
ns
—
35
—
50
ns
—
35
—
50
ns
DEPTH EXPANSION MODE TIMINGS
tXOL
tXOH
tXI
tXIR
tXIS
Read/Write to XO LOW
Read/Write to XO HIGH
XI Pulse Width
XI Recovery Time
XI Set-up Time
35
—
50
—
ns
10
—
10
—
ns
15
—
15
—
ns
NOTE:
1. Guaranteed by design minimum times, not tested.
2751 tbl 07
5.34
4
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5V
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
1.1KΩ
D.U.T.
680Ω
See Figure A
30pF*
2751 tbl 08
2751 drw 03
or equivalent circuit
Figure A. Ouput Load
*Including jig and scope capacitances
FUNCTIONAL DESCRIPTION
Parallel Data Input
The data is written into the FIFO in parallel through the
D0-8 input data lines. A write cycle is initiated on the falling
edge of the Write (W) signal provided the Full Flag (FF) is not
asserted. If the W signal changes from HIGH-to-LOW and the
Full-Flag (FF) is already set, the write line is inhibited internally
from incrementing the write pointer and no write operation
occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. The data is written to the RAM at the write
pointer. On the rising edge of W, the write pointer is
incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (EF)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP. NOTE: SOCP should not be clocked
once the last bit of the last word has been clocked out. If it is,
then two things will occur. One, the SO pin will go High-Z and
two, SOCP will be out of sync with Next Read (NR).
The serial word is shifted out Least Significant Bit first, that
is the first bit will be D0, then D1 and so on up to the serial word
width. The serial word width must be programmed by connecting the appropriate Data Set line (Q4, Q6, Q7 or Q8) to the NR
input. The Data Set lines are taps off a digital delay line.
Selecting one of these taps, programs the width of the serial
word to be read and shifted out.
tRSC
t RS
RS
tRSS
tRSR
W
tRSF1
AEF, EF
tRSF2
HF, FF
t RSS
t RSR
SOCP
t RSQL
t RSQH
Q4, Q6, Q7, Q8
2751 drw 04
Figure 1. Reset
5.34
5
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
t WC
W
t WPW
t WR
D 0–8
t DS
t DH
2751 drw 05
Figure 2. Write Operation
1/f SOCP
0
1
n–1
SOCP
t SOCW
t SOCW
SOX
t SOX
SO (1)
t SOHZ
SO
(2)
t SOLZ
2751 drw 06
t SOPD
Figure 3. Read Operation
NOTES:
1. This timing applies to the Active Device in Width Expansion Mode.
2. This timing applies to Single Device Mode at Empty Boundary (EF = LOW) and the Next Active Device in Width Expansion Mode.
LAST WRITE
IGNORED
WRITE
FIRST READ
0
1
n–1
ADDITIONAL
READS
0
1
FIRST WRITE
n–1
SOCP
W
t WFF
t SOCFF
FF
Figure 4. Full Flag from Last Write to First Read
5.34
2751 drw 07
6
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
LAST READ
NO READ
COMMERCIAL TEMPERATURE RANGES
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
W
0
1
0
n–1
SOCP
1
n–1
(1)
t WEF
tSOCEF
EF
t SOPD
SO
VALID
VALID
2751 drw 08
NOTE:
1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
Figure 5. Empty Flag from Last Read to First Write
DATA IN
W
t WEF
t SOCEF
EF
t REFSO
SOCP
0
1
n–1
(1)
t SOLZ
SO
t SOPD
2751 drw 09
NOTE:
1. SOCP should not be clocked until EF goes HIGH.
Figure 6. Empty Boundary Condition Timing
5.34
7
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
0
COMMERCIAL TEMPERATURE RANGES
1
n–1
SOCP
t SOCFF
t WFF
FF
t WPF
W
t DS
t DH
DATA IN VALID
DATA IN
t SOPD
DATA OUT VALID
SO
2751 drw 10
Figure 7. Full Boundry Condition Timing
W
HALF-FULL (1/2)
HF
HALF-FULL
HALF-FULL +1
t WF
t SOCF
t WF
t SOCF
SOCP
AEF
7/8 FULL
AEF
ALMOST-EMPTY
(1/8 FULL-1)
ALMOST FULL (7/8 FULL + 1)
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
1/8 FULL
2751 drw 11
Figure 8. Half Full, Almost Full and Almost Empty Timings
5.34
8
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
t RTC
t RT
RT
t RTS
t RTR
0
1
SOCP
W
t RTS
FLAG VALID
EF, AEF, HF, FF
2751 drw 12
NOTE:
1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC.
Figure 9. Retransmit
WRITE TO LAST PHYSICAL LOCATION
READ FROM LAST
PHYSICAL LOCATION
W
LAST
LAST -1
0
1
0
1
SOCP
t XOL
t XOL
t XOH
t XOH
XO
2751 drw 13
Figure 10. Expansion-Out
t XI
t XIR
XI
t XIS
Write to first
physical location
W
t XIS
Read from first
physical location
SOCP
2751 drw 14
Figure 11. Expansion-In
5.34
9
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Data Set lines (Q4, Q6, Q7, Q8) go LOW and a new serial word
is started. The Data Set lines then go HIGH on the equivalent
SOCP clock pulse. This continues until the Q line connected
to NR goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SOCP.
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SOCP clock, all of the
PARALLEL DATA IN
D 0-7
SOCP
SERIAL OUTPUT CLOCK
SOX
V CC
1
2
3
4
5
GND
XI
NR
0
SERIAL DATA OUTPUT
SO
6
Q4
7
Q6 Q7 Q8
0
1
2
3
4
5
6
7
0
SOCP
Q4
Q6
Q7
NR
2751 drw 15
Figure 12. Eight-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT —
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs
Internal Status
RS
FL/RT
Reset
0
X
Retransmit
1
0
Read/Write
1
1
0
Mode
XI
Outputs
AEF, EF
FF
HF
Read Pointer
Write Pointer
0
Location Zero
Location Zero
0
1
1
0
Location Zero
Unchanged
X
X
X
Increment(1)
Increment(1)
X
X
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
X
2751 tbl 09
5.34
10
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can
be achieved by using more than one device. By tying the SOX
line of the least significant device HIGH and the SOX of the
subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of SOCP, all lines go
LOW. Just as in the standalone case, on each corresponding
clock cycle, the equivalent Data Set line goes HIGH in order
of least to most significant. When the Data Set line which is
connected to the SOX input of the next device goes HIGH, the
D0 of that device goes HIGH, the cascading from one device
to the next. The Data Set line of the most significant bit
programs the serial word width by being connected to all NR
inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is three stated,
only the device which is currently shifting out is enabled and
driving the 1-bit-bus.
PARALLEL DATA IN
16-BITS WIDE
9
SO
SERIAL OUTPUT CLOCK
GND
D 0-8
SOCP
XI
SO
FIFO #1
D 0-6
GND
XI
FIFO #2
SOX
NR
1
7
SOCP
SOX
V CC
0
SERIAL DATA
OUTPUT
7
Q8
8
NR
9
10
14
15
Q6
0
SOCP
Q 8 OF FIFO #1 AND
SOX OF FIFO #2
Q6 OF FIFO #2 AND
NR OF FIFO #1 AND
FIFO #2
2751 drw 16
Figure 13. Width Wxpansion for 16-bit Parallel Data In. The Parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2.
5.34
11
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode
The IDT72131/41 can be easily adapted to applications
where the requirements are for greater than 2048/4096 words.
Figure 14 demonstrates Depth Expansion using three
IDT72131/41. Any depth can be attained by adding additional
IDT72131/41 operates in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the
First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be
tied to the Expansion In (XI) pin of the next device.
4. External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (i.e., all must be
set to generate the correct composite FF or EF).
5. The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion mode.
D 0-7
XI
FL/RT
SOX
D 0-7
FIFO #1
IDT72141
SO
W
SOCP
XO
Q7
XI
D 0-7
W
NR
VCC
SOCP
VCC
FIFO #2
IDT72141
FL/RT
SOX
SO
W
SOCP
XO
Q7
XI
D 0-7
NR
VCC
SO
VCC
FIFO #3
IDT72141
FL/RT
SOX
SO
W
SOCP
XO
Q7
NR
VCC
2751 drw 17
Figure 14. A 12K x 8 Parallel-In Serial-Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLE —
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
Internal Status
Outputs
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset-First
Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset-All
Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
Read/Write
1
X
(1)
X
X
X
X
Mode
NOTES:
1. XI is connected to XO of previous device.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output, XI = Expansion Input.
5.34
2751 tbl 10
12
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
X
Power
XXX
Speed
X
Package
X
Process/
Temperature
Range
5.34
Blank
Commercial (0°C to +70°C)
P
Plastic DIP
35
50
(50MHz serial shift rate)
(40MHz serial shift rate)
L
Low Power
72131
72141
2048 x 9-Bit Parallel-Serial FIFO
4096 x 9-Bit Parallel-Serial FIFO
Parallel Access Time (tA )
2751 drw 18
13
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