IDT IDT72132L50P Cmos serial-to-parallel fifo 2048 x 9 4096 x 9 Datasheet

CMOS SERIAL-TO-PARALLEL FIFO
2048 x 9
4096 x 9
IDT72132
IDT72142
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 35ns parallel-port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 8, 9, 16-18, and
32-36 bit using Flexshift serial input without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-Port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low-power CMOS
technology
• Available in the 28-pin plastic DIP
• Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
The IDT72132/72142 are high-speed, low-power serial-toparallel FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IDT72132/72142 can be configured with the IDTs parallel-to-serial FIFOs (IDT72131/72141)
for bidirectional serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output
port. Wider and deeper serial-to-parallel data buffers can be
built using multiple IDT72132/72142 chips. IDTs unique
Flexshift serial expansion logic (SIX,
) makes width
expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IDT72132/142 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The Almost-Full (7/8), Half-Full, and Almost Empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72132/72142 is fabricated using IDTs high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
SICP
SIX
SI
NW
D 7 D8
NW
SERIAL INPUT
CIRCUITRY
EF
FLAG
LOGIC
AEF
/HF
FF
NW
RS
FL/RT
XI
RAM ARRAY
2048 x 9
4096 x 9
NEXT WRITE
POINTER
READ
POINTER
R
RESET
LOGIC
EXPANSION
LOGIC
XO/
OE Q 0 -Q 8
Vcc
1
28
GND
2
27
D7
XI
3
26
D8
AEF
4
25
FF
Q0
5
24
RS
23
SI
Q1
7
22
SICP
Q2
Q3
6
P28-1
&
C28-3
FL/RT
8
21
SIX
9
20
OE
Q4
10
19
EF
GND
11
18
XO/HF
R
12
17
GND
Q5
13
16
Q8
Q6
14
15
Q7
2752 drw 01
DIP
TOP VIEW
2752 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
DECEMBER 1996
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.36
DSC-2752/6
1
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
Name
I/O
SI
Serial Input
I
RS
Reset
I
Description
Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input
(SI) pins are tied together and SIX plus D7, D8 determine which device stores the data.
When RS is set LOW, internal READ and WRITE pointers are set to the first location of the
RAM array. HF and FF go HIGH, and AEF, and EF go LOW. A reset is required before an initial
WRITE after power-up. R must be HIGH during an RS cycle.
NW
Next Write
I
SICP
Serial Input Clock
I
Serial data is read into the serial input register on the rising edge of SICP. In both Depth and
Serial Word Width Expansion modes, all of the SICP pins are tied together.
R
Read
I
When READ is LOW, data can be read from the RAM array sequentially, independent of SICP.
In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the
internal READ operation is blocked and Q0-Q8 are in a high impedance condition.
First Load/
Retransmit
I
XI
Expansion In
I
SIX
Serial Input
I
FL/RT
To program the Serial In word width , connect NW with one of the Data Set pins (D7, D8).
This is a dual-purpose input. In the single device configuration (XI grounded), activating
retransmit (FL/RT-LOW) will set the internal READ pointer to the first location. There is no
effect on the WRITE pointer. R must be HIGH and SICP must be LOW before setting FL/RT
LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration,
FL/RT grounded indicates the first activated device.
In the single device configuration, XI is grounded. In depth expansion or daisy chain
expansion, XI is connected to XO (expansion out) of the previous device.
In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin
of all other devices is connected to the D7 or D8 pin of the previous device. For single device
operation, SIX is tied HIGH.
Expansion
OE
Output Enable
I
When OE is set LOW, the parallel output buffers receive data from the RAM array. When OE
is set HIGH, parallel three state buffers inhibit data flow.
Q0–Q8
Output Data
O
Data outputs for 9-bit wide data.
FF
Full Flag
O
When FF goes LOW, the device is full and data must not be clocked by SICP. When FF is
HIGH, the device is not full. See the diagram on page 7 for more details.
EF
Empty Flag
O
When EF goes LOW, the device is empty and further READ operations are inhibited. When
EF is HIGH, the device is not empty.
Almost-Empty/
Almost-Full Flag
O
Expansion Out/
Half-Full Flag
O
D7, D8
Data Set
O
VCC
Power Supply
Single Power Supply of 5V.
GND
Ground
Three grounds at 0V.
AEF
XO/HF
When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
This is a dual-purpose output. In the single device configuration (XI grounded), the device is
more than half full when HF is LOW. In the depth expansion configuration (XO connected to
XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array
is filled.
The appropriate Data Set pin (D7, D8 ) is connected to NW to program the Serial In data word
width. For example: D7 - NW programs a 8-bit word width, D8 - NW programs a 9-bit word
width, etc.
2752 tbl 01
STATUS FLAGS
Number of Words in FIFO
IDT72132
IDT72142
FF
AEF
HF
EF
0
0
H
L
H
L
1-255
1-511
H
L
H
H
256-1024
512-2048
H
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L
H
2048
4096
L
L
L
H
2752 tbl 02
5.36
2
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
°C
TBIAS
Temperature
Under Bias
–55 to +125
°C
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output
Current
50
mA
Symbol
Parameter
Min.
Typ.
Max. Unit
4.5
5.0
5.5
V
0
0
0
V
VCC
Commercial Supply
Voltage
GND
Supply Voltage
VIH
Input High Voltage
Commercial
2.0
—
—
V
VIL(1)
Input Low Voltage
—
—
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2752 tbl 04
NOTE:
2752 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
10
pF
COUT
Output Capacitance
VOUT = 0V
12
pF
NOTE:
1. This parameter is sampled and not 100% tested.
2752 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
IDT72132/IDT72142
Commercial
Symbol
IIL
(1)
Parameter
Input Leakage Current
(Any Input)
Min.
Typ.
Max.
Unit
–1
—
1
µA
IOL(2)
Output Leakage Current
–10
—
10
µA
VOH
Output Logic "1" Voltage,
IOUT = -2mA
2.4
—
—
V
VOL
Output Logic "0" Voltage,
IOUT = 8mA
—
—
0.4
V
Power Supply Current
—
90
140
mA
ICC2
Average Standby Current
(R = RS = FL/RT = VIH)
(SICP = VIL)
—
8
12
mA
ICC3(L)(3,4)
Power Down Current
—
—
2
mA
ICC1(3)
(3)
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≤ VIL, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open.
2752 tbl 06
5.36
3
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
Symbol
Parameter
tS
Parallel Shift Frequency
tSICP
Serial-InShift Frequency
PARALLEL OUTPUT TIMINGS
tA
Access Time
tRR
Read Recovery Time
tRPW
Read Pulse Width
tRC
Read Cycle Time
tRLZ
Read Pulse LOW to Data Bus at Low-Z(1)
tRHZ
Read Pulse HIGH to Data Bus at High-Z(1)
tDV
Data Valid from Read Pulse HIGH
tOEHZ
Output Enable to High-Z (Disable)(1)
tOELZ
Output Enable to Low-Z (Enable)(1)
tAOE
Output Enable to Data Valid (Q0-8)
SERIAL INPUT TIMINGS
tSIS
Serial Data in Set-Up Time to SICP Rising Edge
tSIH
Serial Data in Hold Time to SICP Rising Edge
tSIX
SIX Set-Up Time to SICP Rising Edge
tSICW
Serial-In Clock Width HIGH/LOW
FLAG TIMINGS
tSICEF
SICP Rising Edge (Last Bit - First Word) to EF HIGH
tSICFF
SICP Rising Edge (Bit 1 - Last Word) to FF LOW
tSICF
SICP Rising Edge to HF, AEF
tRFFSI
Recovery Time SICP After FF Goes HIGH
tREF
Read LOW to EF LOW
tRFF
Read HIGH to FF HIGH
tRF
Read HIGH to Transitioning HF and AEF
tRPE
Read Pulse Width After EF HIGH
RESET TIMINGS
tRSC
Reset Cycle Time
tRS
Reset Pulse Width
tRSS
Reset Set-up Time
tRSR
Reset Recovery Time
tRSF1
Reset to EF and AEF LOW
tRSF2
Reset to HF and FF HIGH
tRSDL
Reset to D LOW
tPOI
SICP Rising Edge to D
RETRANSMIT TIMINGS
tRTC
Retransmit Cycle Time
tRT
Retransmit Pulse Width
tRTS
Retransmit Set-up Time
tRTR
Retransmit Recovery Time
DEPTH EXPANSION MODE TIMINGS
tXOL
Read/Write to XO LOW
tXOH
Read/Write to XO HIGH
tXI
XI Pulse Width
tXIR
XI Recovery Time
tXIS
XI Set-up Time
Commercial
IDT72132L35
IDT72132L50
IDT72142L35
IDT72142L50
Min.
Max.
Min.
Max.
—
22.2
—
15
—
50
—
40
NOTE:
1. Guaranteed by design minimum times, not tested
Unit
MHz
MHz
—
10
35
45
5
—
5
—
5
—
35
—
—
—
—
20
—
15
—
20
—
15
50
65
10
—
5
—
5
—
50
—
—
—
—
30
—
15
—
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
0
5
8
—
—
—
—
15
0
5
10
—
—
—
—
ns
ns
ns
ns
—
—
—
15
—
—
—
35
45
30
45
—
30
30
45
—
—
—
—
15
—
—
—
50
65
40
65
—
45
45
65
—
ns
ns
ns
ns
ns
ns
ns
ns
45
35
35
10
—
—
20
5
—
—
—
—
45
45
—
17
65
50
50
15
—
—
35
5
—
—
—
—
65
65
—
20
ns
ns
ns
ns
ns
ns
ns
ns
45
35
35
10
—
—
—
—
65
50
50
15
—
—
—
—
ns
ns
ns
ns
—
—
35
10
16
40
40
—
—
—
—
—
50
10
15
50
50
—
—
—
ns
ns
ns
ns
ns
2752 tbl 07
5.36
4
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
5V
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.1K
Ω
1.5V
Output Load
See Figure A
D.U.T.
2752 tbl 08
30pF*
680Ω
2752 drw 03
or equivalent circuit
Figure A. Output Load
*Includies jig and scope capacitances
FUNCTIONAL DESCRIPTION
Serial Data Input
The serial data is input on the SI pin. The data is clocked
in on the rising edge of SICP providing the Full Flag (FF) is not
asserted. If the Full Flag is asserted then the next parallel data
word is inhibited from moving into the RAM array. NOTE:
SICP should not be clocked once the last bit of the last word
has been shifted in, as indicated by NW HIGH and FF LOW.
If it is, then the input data will be lost.
The serial word is shifted in Least Significant Bit first. Thus,
when the FIFO is read, the Least Significant Bit will come out
on Q0 and the second bit is on Q1 and so on. The serial word
width must be programmed by connecting the appropriate
Data Set line (D7, D8) to the NW input. The data set lines are
taps off a digital delay line. Selecting one of these taps
programs the width of the serial word to be written in.
Parallel Data Output
A read cycle is initiated on the falling edge of Read (R)
provided the Empty Flag is not set. The output data is
accessed on a first-in/first-out basis, independent of the
ongoing write operations. The data is available tA after the
falling edge of R and the output bus Q goes into high impedance after R goes HIGH.
Alternately, the user can access the FIFO by keeping R
LOW and enabling data on the bus by asserting Output Enable
(OE). When R is LOW, the OE signal enables data on the
output bus. When R is LOW and OE is HIGH, the output bus
is three-stated. When R is HIGH, the output bus is disabled
irrespective of OE.
t RSC
t RS
RS
t RSR
t RSS
0
n-1
SICP
(1)
t RSS
R
t RSF1
AEF, EF
t RSF2
HF, FF
t RSDL
t PDI
D7 ,D8
2752 drw 04
NOTE:
1. Input bits are numbered 0 to n-1. D7 and D8 correspond to n=8 and n=9 respectively
Figure 1. Reset
5.36
5
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
t SICW
0
t SICW
1
n–1
2
(1)
SICP
1/t SICP
SIX
t SIX
SI
t SIS
t SIH
2752 drw 05
Figure 2. Write Operation
NOTE:
1. Input bits are numbered 0 to n-1.
t RC
R
t RPW
t RR
Q0–8
VALID DATA
t RLZ
t DV
tA
t RHZ
2752 drw 06
Figure 3. Read Operation
t RC
t RR
R
TERMINATE READ CYCLE
OE
tA
t RLZ
Q0–8
SECOND READ BY CONTROLLINGOE
t AOE
t OELZ
t OEHZ
DATA 1
t DV
DATA 1
2752 drw 07
Figure 4. Output Enable Timings
5.36
6
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
LAST WRITE
NO WRITE
COMMERCIAL TEMPERATURE RANGES
FIRST READ
ADDITIONAL
READS
FIRST WRITE
R
0
1
0
n–1
SICP
1
n–1
(1)
t SICFF
t RFF
FF
2752 drw 08
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 5. Full Flag from Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
0
1
ADDITIONAL
WRITES
n–1
0
1
FIRST READ
n–1
SICP
R
t REF
t SICEF
EF
tA
DATA OUT
VALID
VALID
2752 drw 09
Figure 6. Empty Flag from Last Read to First Write
FIRST SERIAL-IN WORD
0
1
SECOND SERIAL-IN WORD
n–1
0
1
n–1
0
SICP
t SICEF
EF
t RPE
R
tA
DATA OUT
2752 drw 10
Figure 7. Empty Boundry Condition Timing
5.36
7
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
R
t RFF
FF
t SICFF
t RFFSI
SICP
0
1
n–1
(1)
t SIS
SI
tA
DATA OUT
2752 drw 11
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 8. Full Boundry Condition Timing
0
1
n–2
n–1
SICP
HF
HALF-FULL
HALF-FULL
HALF_FULL + 1
t SICF
t RF
t SICF
t RF
R
AEF
7/8 FULL
AEF
ALMOST-EMPTY
(1/8 FULL-1)
7/8 FULL
ALMOST FULL (7/8 + 1)
ALMOST-EMPTY
(1/8 FULL-1)
1/8 FULL
2752 drw 12
Figure 9. Half Full, Almost Full and Almost Empty Timings
t RTC
t RT
RT
t RTS
t RTR
0
1
SICP
R
t RTS
EF, AEF, HF, FF
FLAG VALID
2752 drw 13
NOTE:
1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC.
Figure 10. Retransmit
5.36
8
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
WRITE TO LAST PHYSICAL LOCATION
0
1
n–1
SICP
READ FROM LAST
PHYSICAL LOCATION
R
t XOL
t XOH
t XOL
t XOH
XO
2752 drw 14
Figure 11. Expansion-Out
t XI
t XIR
XI
t XIS
0
1
n–1
SICP
t XIS
R
Write to first
physical location
Read from
physical location
2752 drw 15
Figure 12. Expansion-In
5.36
9
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SIX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SICP clock, both of the
Data Set lines (D7, D8) go LOW and a new serial word is
started. The Data Set lines then go HIGH on the equivalent
SICP clock pulse. This continues until the D line connected to
NW goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SICP.
SERIAL DATA IN
SI
SICP
SERIAL INPUT CLOCK
VCC
Q 0-8
SIX
1
2
3
4
5
6
GND
XI
NW
0
PARALLEL DATA OUTPUT
7
D7 D8
8
0
1
2
3
4
5
6
7
0
8
SICP
D7
D8
NW
2752 drw 16
Figure 13. Nine-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs
Internal Status
Outputs
RS
FL/RT
XI
Read Pointer
Write Pointer
AEF, EF
FF
HF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
(1)
X
X
Mode
Read/Write
1
1
0
(1)
Increment
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
Increment
X
2752 tbl 09
5.36
10
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can
be achieved by using more than one device. By tying the SIX
line of the least significant device HIGH and the SIX of the
subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of SICP, both the
Data Set lines go LOW. Just as in the standalone case, on
each corresponding clock cycle, the equivalent Data Set line
goes HIGH in order of least to most significant.
SERIAL DATA IN
8
XI
SI
Q 0-7
XI
8
SI
Q 0-7
PARALLEL
DATA OUT
8
SICP
SERIAL-IN CLOCK
SICP
FIFO #1
SIX
VCC
SIX
NW
0
1
FIFO #2
D7
7
NW
8
9
10
14
D7
15
0
SOCP
D 7 OF FIFO #1
AND SIX OF
FIFO #2
D 7 OF FIFO #2
AND NW TO
FIFO #1 AND
FIFO #2
2752 drw 17
Figure 14. Serial-In to Parallel-Out Data of 16 Bits
5.36
11
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode
The IDT72132/42 can be easily adapted to applications
where the requirements are for greater than 2048/4096 words.
Figure 15 demonstrates Depth Expansion using three
IDT72132/42. Any depth can be attained by adding additional
IDT72132/42 operates in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the
First Load (FL) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin and Expansion In (XI) pin
of each device must be tied together.
4. External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (i.e., all must be
set to generate the correct composite (FF) or (EF).
5. The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion mode.
Q 0-7
Q 0-7
SIX
VCC
R
FIFO #1
IDT72142
FL/RT
SI
SICP
SICP
VCC
FIFO #2
IDT72142
SIX
FL/RT
SI
XO XI
D7
XI
Q 0-7
XO
R
NW
R
D7
SICP
NW
2752 drw 18
SI
Figure 15. An 8K x 8 Serial-In Parallel-Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLE —
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
Internal Status
Outputs
RS
FL/RT
XI
Read Pointer
Write Pointer
EF
FF
Reset-First
Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset all
Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
Read/Write
1
X
(1)
X
X
X
X
Mode
NOTES:
1. XI is connected to XO of the previous device.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output, XI = Expansion Input.
5.36
2752 tbl 10
12
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
VCC
SI
SIX
D7
SI
SIX
D7
NW
SICP
SICP
R
CC
R
Q 0-7
XI XO
XI XO
V
SIX SI D7 XO XI
SERIAL
INPUT
CLOCK
R
Q 0-7
XI XO
D7
NW
SICP
Q 0-7
SI
SIX
NW
NW
SICP
SIX SI D7 XO XI
SIX SI D7 XO XI
NW
SICP
NW
SICP
R
R
R
Q0-7
Q0-7
Q0-7
P0-7
P8-15
P16-23
READ
2752 drw 19
PARALLEL DATA OUT
Figure 16. An 8K x 24 Serial-In, Parallel-Out FIFO Using Six IDT72142s
ORDERING INFORMATION
IDT XXXXX
Device
Type
X
Power
XXX
Speed
X
Package
X
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
P
Plastic DIP
35
50
5.36
(50MHz serial shift rate)
(40MHz serial shift rate)
Parallel Access Time (tA)
L
Low Power
72132
72142
2048 x 9-Bit Serial-Parallel FIFO
4096 x 9-Bit Serial-Parallel FIFO
2752 drw 20
13
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