IDT IDT72211L25PFI Cmos syncfifoo 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 Datasheet

CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9 and 8,192 x 9
IDT72421, IDT72201
IDT72211, IDT72221
IDT72231, IDT72241
IDT72251
FEATURES:
DESCRIPTION:
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The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. These devices have a 64, 256, 512, 1,024,
2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are
applicable for a wide variety of data buffering needs such as graphics, local area
networks and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).
Data is written into the Synchronous FIFO on every rising clock edge when the
write enable pins are asserted. The output port is controlled by another clock
pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An output enable pin
(OE) is provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the load pin (LD).
These FIFOs are fabricated using IDT’s high-speed submicron CMOS
technology.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 x 9-bit organization (IDT72421)
256 x 9-bit organization (IDT72201)
512 x 9-bit organization (IDT72211)
1,024 x 9-bit organization (IDT72221)
2,048 x 9-bit organization (IDT72231)
4,096 x 9-bit organization (IDT72241)
8,192 x 9-bit organization (IDT72251)
10 ns read/write cycle time
Read and Write Clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set
to any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in the 32-pin plastic leaded chip carrier (PLCC) and
32-pin Thin Quad Flat Pack (TQFP)
For through-hole product please see the IDT72420/72200/72210/
72220/72230/72240 data sheet
Industrial temperature range (–40°°C to +85°°C) is available
FUNCTIONAL BLOCK DIAGRAM
D0 - D8
WCLK
WEN1
WEN2
LD
INPUT REGISTER
OFFSET REGISTER
EF
PAE
PAF
FF
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
OE
2655 drw01
Q0 - Q8
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2002
1
 2002
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2655/2
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D1
1
24
WEN1
D0
2
23
PAF
3
22
PAE
GND
4
21
WCLK
WEN2/LD
VCC
D8
2
D6
3
D7
4
D5
D3
D4
32 31 30 29 28 27 26 25
D2
INDEX
RS
D7
D8
D6
D5
D4
INDEX
D3
D2
PIN CONFIGURATION
32 31 30
1
D1
5
29
RS
D0
6
28
WEN1
PAF
7
27
WCLK
WEN2/LD
PAE
8
26
GND
9
25
REN1
10
24
VCC
Q8
Q7
REN1
6
19
Q8
Q7
RCLK
REN2
7
18
Q6
RCLK
11
23
8
17
Q5
REN2
12
22
Q6
OE
13
21
Q5
20
TQFP (PR32-1, order code: PF)
TOP VIEW
Q4
Q3
Q2
2655 drw 02
Q1
14 15 16 17 18 19 20
EF
Q4
Q3
Q2
Q1
FF
Q0
OE
EF
9 10 11 12 13 14 15 16
FF
Q0
5
2655 drw02a
PLCC (J32-1, order code: J)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
D0-D8
Data Inputs
RS
Reset
WCLK
WEN1
WEN2/
LD
Q0-Q8
RCLK
Write Enable 2/
Load
REN1
Data Outputs
Read Clock
Read Enable 1
REN2
Read Enable 2
OE
Output Enable
EF
Empty Flag
PAE
FF
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
V CC
GND
Power
Ground
PAF

Write Clock
Write Enable 1
I/O
Description
I Data inputs for a 9-bit bus.
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW,
data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write
enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW.
I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is HIGH
at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a control
to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must
be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is
LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the
programmable flag offsets.
O Data outputs for a 9-bit bus.
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the
FIFO is not empty. EF is synchronized to RCLK.
O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is Empty+7. PAE is synchronized to RCLK.
O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is Full-7. PAF is synchronized to WCLK.
O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
TSTG
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
IOUT
DC Output Current
Com'l & Ind'l
–0.5 to +7.0
Unit
V
–55 to +125
°C
–50 to +50
mA
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RECOMMENDED OPERATING
CONDITIONS
Symbol
VCC
GND
VIH
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIL
TA
TA
Parameter
Supply Voltage
Commercial/Industrial
Supply Voltage
Input High Voltage
Commercial/Industrial
Input Low Voltage
Commercial/Industrial
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
4.5
Typ. Max.
5.0
5.5
Unit
V
0
2.0
0
—
0
—
V
V
—
—
0.8
V
0
—
+70
°C
–40
—
+85
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
IDT72421
IDT72201
IDT72211
IDT72221
IDT72231
IDT72241
Com'l and Ind'l(1)
tCLK = 10, 15, 25 ns
Symbol
Parameter
Min.
Typ.
Max.
IDT72251
Com'l and Ind'l(1)
tCLK = 10, 15, 25 ns
Min.
Typ.
Max.
ILI(2)
Input Leakage Current (Any Input)
–1
—
1
–1
—
1
ILO(3)
Output Leakage Current
–10
—
10
–10
—
10
VOH
Output Logic “1” Voltage, IOH = –2mA
2.4
—
—
2.4
—
—
Output Logic “0” Voltage, IOL = 8mA
—
—
0.4
—
—
0.4
Active Power Supply Current
—
—
35
—
—
50
Standby Current
—
—
5
—
—
5
VOL
ICC1
(4,5,6)
ICC2(4,7)
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 1.7 + 0.7*fS + 0.02*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

3
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tPAF
tPAE
tSKEW1
tSKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width(2)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(3)
Output Enable to Output Valid
Output Enable to Output in High-Z(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Programmable Almost-Full Flag
Read Clock to Programmable Almost-Empty Flag
Skew time between Read Clock & Write Clock for
Empty Flag & Full Flag
Skew time between Read Clock & Write Clock for
Almost-Empty Flag & Programmable Almost-Full Flag
Com'l & Ind'l(1)
IDT72421L15
IDT72201L15
IDT72211L15
IDT72221L15
IDT72231L15
IDT72241L15
IDT72251L15
Min.
Max.
—
66.7
2
10
15
—
6
—
6
—
4
—
1
—
4
—
1
—
15
—
10
—
10
—
—
15
0
—
3
8
3
8
—
10
—
10
—
10
—
10
6
—
Commercial
IDT72421L10
IDT72201L10
IDT72211L10
IDT72221L10
IDT72231L10
IDT72241L10
IDT72251L10
Min.
Max.
—
100
2
6.5
10
—
4.5
—
4.5
—
3
—
0.5
—
3
—
0.5
—
10
—
8
—
8
—
—
10
0
—
3
6
3
6
—
6.5
—
6.5
—
6.5
—
6.5
5
—
14
—
15
—
Com'l & Ind'l(1)
IDT72421L25
IDT72201L25
IDT72211L25
IDT72221L25
IDT72231L25
IDT72241L25
IDT72251L25
Min.
Max.
—
40
2
15
25
—
10
—
10
—
6
—
1
—
6
—
1
—
15
—
15
—
15
—
—
25
0
—
3
13
3
13
—
15
—
15
—
15
—
15
10
—
18
—
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
1.1K
D.U.T.
680Ω
CAPACITANCE (Ta = +25°C, f = 1.0MHz)
Symbol
CIN(2)
COUT(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
10
10
Unit
pF
pF
2655 drw 03
or equivalent circuit
NOTES:
1. With output deselected (OE ≥ VIH).
2. Characterized values, not currently tested.

30pF*
Figure 1. Output Load
*includes jig and scope capacitances
4
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
SIGNAL DESCRIPTIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows depth expansion.
If Write Enable 2/Load (WEN2/LD) is set HIGH at Reset (RS = LOW), this pin
operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock (WCLK). Data is stored in the RAM array sequentially and
independently of any ongoing read operation.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when the Write Enable
2/Load (WEN2/LD) is set LOW at Reset (RS=LOW). The IDT72421/72201/
72211/72221/72231/72241/72251 devices contain four 8-bit offset registers
which can be loaded with data on the inputs, or read on the outputs. See Figure
3 for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when the Write Enable
1 (WEN1) and Write Enable 2/Load (WEN2/LD) are set LOW, data on the inputs
D is written into the Empty (Least Significant Bit) Offset register on the first LOWto-HIGH transition of the Write Clock (WCLK). Data is written into the Empty (Most
Significant Bit) Offset register on the second LOW-to-HIGH transition of the Write
Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourth
transition. The fifth transition of the Write Clock (WCLK) again writes to the Empty
(Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the Write Enable 2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, the Write
Enable 1 (WEN1) is LOW, the next offset register in sequence is written.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full flag (PAF) will be reset
to HIGH after tRSF. The Empty Flag (EF) and Programmable Almost-Empty
flag (PAE) will be reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of WCLK. The Full Flag (FF) and Programmable Almost-Full flag
(PAF) are synchronized with respect to the LOW-to-HIGH transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE 1 (WEN1)
If the FIFO is configured for programmable flags, Write Enable 1 (WEN1)
is the only enable control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM array on the LOWto-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion, there are two enable control pins. See Write Enable 2 paragraph
below for operation in this configuration.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty flag
(PAE) are synchronized with respect to the LOW-to-HIGH transition of RCLK.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLES (REN1, REN2)
When both Read Enables (REN1, REN2) are LOW, data is read from the
RAM array to the output register on the LOW-to-HIGH transition of the Read
Clock (RCLK).
When either Read Enable (REN1, REN2) is HIGH, the output register holds
the previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid
read can begin. The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
LD
WEN1
0
0
0
1
1
0
No Operation
Write Into FIFO
1
1
No Operation
WCLK
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
NOTE:
1. For the purposes of this table, WEN2 = VIH.
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register

5
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
The contents of the offset registers can be read on the output lines when the
Write Enable 2/Load (WEN2/LD) pin is set LOW and both Read Enables (REN1,
REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the
Read Clock (RCLK).
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A read and write should not be performed simultaneously to the offset
registers.
IDT72421 - 64 x 9-BIT
8
IDT72201 - 256 x 9-BIT
8
6 5
0
Empty Offset (LSB) Reg.
7
Default Value 007H
Default Value 007H
8
6 5
8
0
8
0
8
0
7
8
0
8
0
8
0
IDT72221 - 1,024 x 9-BIT
IDT72211 - 512 x 9-BIT
7
7
0
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Default Value 007H
1
8
0
Full Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
8
0
Empty Offset (LSB) Reg.
8
0
0
1
(MSB)
(MSB)
00
0
8
8
0
7
7
8
Default Value 007H
7
8
0
1
(MSB)
0
00
8
2
0
0
7
Empty Offset (LSB) Reg.
Default Value 007H
8
Default Value 007H
3
0
8
4
(MSB)
8
7
00000
0
8
Full Offset (LSB)
8
3
7
0
Full Offset (LSB)
Default Value 007H
0
0
(MSB)
0000
0
2
0
Default Value 007H
8
Full Offset (LSB) Reg.
Default Value 007H
8
7
Empty Offset (LSB)
000
7
8
Empty Offset (LSB)
(MSB)
8
IDT72251 8,192 x 9-BIT
IDT72241 - 4,096 x 9-BIT
0
0
1
(MSB)
IDT72231 - 2,048 x 9-BIT
8
0
Full Offset (LSB) Reg.
Full Offset (LSB)
Default Value 007H
Default Value 007H
0
8
4
0
(MSB)
(MSB)
(MSB)
000
0000
00000
2655 drw 05
Figure 3. Offset Register Location and Default Values

6
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
(1,024-m) writes for the IDT72221, (2,048-m) writes for the IDT72231, (4,096m) writes for the IDT72241, and (8,192-m) writes for the IDT72251. The offset
“m” is defined in the Full offset registers.
If there is no Full offset specified, the Programmable Almost-Full flag (PAF)
will go LOW at Full-7 words.
The Programmable Almost-Full flag (PAF) is synchronized with respect to
the LOW-to-HIGH transition of the Write Clock (WCLK).
OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
will go LOW after 64 writes for the IDT72421, 256 writes for the IDT72201, 512
writes for the IDT72211, 1,024 writes for the IDT72221, 2,048 writes for the
IDT72231, 4,096 writes for the IDT72241, and 8,192 writes for the IDT72251.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the read
pointer is "n+1" locations less than the write pointer. The offset "n" is defined
in the Empty Offset registers. If no reads are performed after Reset the
Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the
IDT72421/72201/72211/72221/72231/72241/72251.
If there is no Empty offset specified, the Programmable Almost-Empty flag
(PAE) will go LOW at Empty+7 words.
The Programmable Almost-Empty flag (PAE) is synchronized with respect
to the LOW-to-HIGH transition of the Read Clock (RCLK).
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. If no reads are performed after Reset (RS),
the Programmable Almost-Full flag (PAF) will go LOW after (64-m) writes for the
IDT72421, (256-m) writes for the IDT72201, (512-m) writes for the IDT72211,
DATA OUTPUTS (Q0 - Q8)
Data outputs for a 9-bit wide data.
TABLE 1 — STATUS FLAGS
NUMBER OF WORDS IN FIFO
IDT72201
0
1 to n (1)
IDT72421
0
1 to n (1)
(n+1) to (64-(m+1))
(64-m)(2) to 63
64
(n+1) to (256-(m+1))
(256-m)(2) to 255
256
IDT72211
0
1 to n (1)
FF
H
H
PAF
H
H
PAE
L
L
EF
L
H
(n+1) to (512-(m+1))
(512-m)(2) to 511
512
H
H
L
H
L
L
H
H
H
H
H
H
NUMBER OF WORDS IN FIFO
IDT72221
IDT72231
IDT72241
IDT72251
FF
PAF
PAE
EF
0
0
0
0
H
H
L
L
H
H
L
H
H
H
H
H
(1)
(1)
1 to n
1 to n
(n+1) to (1,024-(m+1))
(2)
(n+1) to (2,048-(m+1))
(2)
(1)
(1)
1 to n
1 to n
(n+1) to (4,096-(m+1))
(2)
(2)
(1,024-m) to 1,023
(2,048-m) to 2,047
(4,096-m) to 4,095
(8,192-m) to 8,191
H
L
H
H
1,024
2,048
4,096
8,192
L
L
H
H
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)

(n+1) to (8,192-(m+1))
7
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
RS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN1, REN2
WEN1
WEN2/LD (1)
tRSF
EF, PAE
tRSF
FF, PAF
tRSF
OE = 1
(2)
Q0 - Q8
OE = 0
2655 drw 06
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable
flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
tCLK
tCLKH
tCLKL
WCLK
tDH
tDS
D0 - D8
DATA IN VALID
tENS
tENH
NO OPERATION
WEN1
tENS
tENH
WEN2/
(If Applicable)
NO OPERATION
tWFF
tWFF
FF
tSKEW1(1)
RCLK
REN1,
REN2
2655 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing

8
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN1,
REN2
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 - Q8
tOLZ
tOHZ
tOE
OE
(1)
tSKEW1
WCLK
WEN1
2655 drw 08
WEN2
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
WCLK
tDS
D0 - D8
D1
tENS
D2
D3
D0 (First Valid Write)
WEN1
tENS
WEN2
(If Applicable)
tFRL
(1)
tSKEW1
RCLK
tREF
EF
tENS
REN1,
REN2
tA
Q0 - Q8
tA
D0
tOLZ
D1
tOE
OE
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
2655 drw 09
Figure 7. First Data Word Latency Timing

9
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
NO WRITE
NO WRITE
WCLK
tSKEW1
tDS
tSKEW1
D0 - D8
tWFF
tWFF
tWFF
FF
(1)
tENS
tENH
tENS
tENS
tENH
tENS
WEN1
(1)
WEN2
(If Applicable)
RCLK
tENH
tENS
REN1,
REN2
tENS
tENH
tA
OE LOW
tA
Q0 - Q8 DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2655 drw 10
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLK
tDS
D0 - D8
tDS
DATA WRITE 1
tENS
DATA WRITE 2
tENH
tENS
tENH
tENS
tENH
WEN1
tENS
tENH
WEN2
(If Applicable)
(1)
tSKEW1
(1)
tFRL
tSKEW1
tFFL
RCLK
tREF
tREF
tREF
EF
REN1,
REN2
OE LOW
tA
Q0 - Q8 DATA IN OUTPUT REGISTER
DATA READ
2655 drw 11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK+ tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing

10
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tCLKH
tCLKL
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
(4)
WCLK
tENS
tENH
tENS
tENH
WEN1
WEN2
(If Applicable)
tPAF
PAF
Full - (m+1) words in FIFO
(1)
(2)
Full - m words in FIFO
(3)
tSKEW2
tPAF
RCLK
tENH
tENS
REN1,
REN2
2655 drw 12
NOTES:
1. m = PAF offset .
2. 64-m words in FIFO for IDT72421, 256-m words for IDT72201, 512-m words for IDT72211, 1,024-m words for IDT72221, 2,048-m words for IDT72231, 4,096-m words for IDT72241,
and 8,192-m words for IDT72251.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
tCLKH
tCLKL
WCLK
tENS
tENH
tENS
tENH
WEN1
WEN2
(If Applicable)
PAE
n+1 words in FIFO
n words in FIFO (1)
tSKEW2 (2)
tPAE
tPAE
(3)
RCLK
tENS
REN1,
REN2
tENH
2655 drw 13
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and
the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing

11
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
tENS
tENH
LD
tENS
WEN1
tDS
tDH
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
2655 drw 14
Figure 12. Write Offset Registers Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
LD
tENS
REN1,
REN2
tA
Q0 - Q7
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
Figure 13. Read Offset Registers Timing

12
2655 drw15
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72421/72201/72211/72221/72231/72241/72251 may be used
when the application requirements are for 64/256/512/1,024/2,048/4,096/
8,192 words or less. When these FIFOs are in a Single Device Configuration,
the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset
so that the pin operates as a control to load and read the programmable flag
offsets.
DEPTH EXPANSION - The IDT72421/72201/72211/72221/72231/72241/
72251 can be adapted to applications when the requirements are for greater
than 64/256/512/1,024/2,048/4,096/8,192 words. The existence of two
enable pins on the read and write port allow depth expansion. The Write
Enable 2/Load pin is used as a second write enable in a depth expansion
configuration thus the Programmable flags are set to the default values. Depth
expansion is possible by using one enable input for system control while the
other enable input is controlled by expansion logic to direct the flow of data. A
typical application would have the expansion logic alternate data access from
one device to the next in a sequential manner. These devices operate in the
Depth Expansion configuration when the following conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a
second Write Enable.
2. External logic is used to control the flow of data.
Please see the Application Note "DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details
of this configuration.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should be created for each
of the endpoint status flags (EF and FF). The partial status flags (AE and AF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
width by using two IDT72421/72201/72211/72221/72231/72241/72251s.
Any word width can be attained by adding additional IDT72421/72201/72211/
72221/72231/72241/72251s.
When these FIFOs are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
RESET (RS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
IDT
72421
72201
72211
72221
72231
72241
72251
WRITE ENABLE 1 (WEN1)
WRITE ENABLE 2/LOAD (WEN2/LD)
DATA IN (D0 - D8)
FULL FLAG (FF)
PROGRAMMABLE ALMOST-FULL (PAF)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
DATA OUT (Q0 - Q8)
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY (PAE)
2655 drw 16
READ ENABLE 2 (REN2)
Figure 14. Block Diagram of Single 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 Synchronous FIFO
RESET (RS)
RESET (RS)
DATA IN (D)
18
9
9
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE1 (WEN1)
WRITE ENABLE2/LOAD (WEN2/LD)
FULL FLAG (FF) #1
FULL FLAG (FF) #2
READ ENABLE (REN)
IDT
72421
72201
72211
72221
72231
72241
72251
PROGRAMMABLE (PAF)
IDT
72421
72201
72211
72221
72231
72241
72251
9
READ ENABLE 2 (REN2)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
9 DATA OUT (Q)
READ ENABLE 2 (REN2)
Figure 15. Block Diagram of 64 x 18, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration

13
18
2655 drw 17
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
Device Type Power Speed Package
X
Process/
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (›40° to +85°C)
J
PF
Plastic Leaded Chip Carrier (PLCC, J32-1)
Thin Quad Flat Pack (TQFP, PR32-1)
10
15
25
Commercial Only
Commercial & Industrial
Commercial & Industrial
L
Low Power
72421
72201
72211
72221
72231
72241
72251
64 x 9  SyncFIFO
256 x 9  SyncFIFO
512 x 9  SyncFIFO
1,024 x 9  SyncFIFO
2,048 x 9  SyncFIFO
4,096 x 9  SyncFIFO
8,192 x 9  SyncFIFO
Clock Cycle Time (tCLK)
Speed in Nanoseconds
2655 drw18
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
DATASHEET DOCUMENT HISTORY
10/03/2000
05/01/2001
pgs. 2, 3, 4 and 14.
pgs. 1, 2, 3, 4 and 14.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
14
for Tech Support:
408-330-1753
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