IDT IDT723611 Cmos syncfifo 64 x 36 Datasheet

IDT723611
CMOS SyncFIFO
64 x 36
Integrated Device Technology, Inc.
• Fast access times of 10ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• Low-power advanced CMOS technology
• Industrial temperature range (-40oC to +85oC) is available, tested to military elecrical specifications
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• 64 x 36 storage capacity
• Synchronous data buffering from Port A to Port B
• Mailbox bypass register in each direction
• Programmable Almost-Full (AF) and Almost-Empty (AE)
flags
• Microprocessor Interface Control Logic
• Full Flag (FF) and Almost-Full (AF) flags synchronized by
CLKA
• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
• Supports clock frequencies up to 67MHz
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power,
CMOS Synchronous (clocked) FIFO memory which supports
clock frequencies up to 67MHz and has read access times as
fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port
A to Port B. The FIFO has flags to indicate empty and full
conditions, and two programmable flags, Almost-Full (AF) and
Almost-Empty (AE), to indicate when a selected number of
words is stored in memory. Communication between each
port can take place through two 36-bit mailbox registers. Each
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
Port-A
Control
Logic
Reset
Logic
EVEN
PGB
Parity
Generation
ODD/
Mail 1
Register
Input
Register
RST
MBF1
PEFB
Parity
Gen/Check
64 x 36
SRAM
•
Output
Register
W/RA
ENA
MBA
36
36
A0 - A35
Write
Pointer
FF
AF
Read
Pointer
B0 - B35
EF
AE
Status Flag
Logic
FIFO
Programmable
Flag Offset
Registers
FS0
FS1
PGA
PEFA
MBF2
Parity
Gen/Check
Mail 2
Register
CLKB
Port-B
Control
Logic
CSB
W/RB
ENB
MBB
3024 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1997 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3024/4
1
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
chronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The Full-Flag (FF) and Almost-Full (AF) flag of the FIFO are
two-stage synchronized to the port clock that writes data into
its array (CLKA). The Empty Flag (EF) and Almost-Empty (AE)
flag of the FIFO are two-stage synchronized to the port clock
that reads data from its array.
The IDT723611 is characterized for operation from 0°C to
70°C.
DESCRIPTION (CONTINUED)
mailbox register has a flag to signal when new mail has been
stored. Parity is checked passively on each port and may be
ignored if not desired. Parity generation can be selected for
data read from each port. Two or more devices may be used
in parallel to create wider data paths.
The IDT723611 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asyn-
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
A24
A25
A26
VCC
A27
A28
A29
GND
A30
A31
A32
A33
A34
A35
GND
B35
B34
B33
B32
B31
B30
GND
B29
B28
B27
VCC
B26
B25
B24
B23
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
VCC
B6
B5
B4
B3
GND
B2
B1
B0
EF
AE
NC
NC
CSB
PGB
VCC
W/RB
CLKB
ENB
MBF1
PEFB
RST
GND
NC
NC
NC
NC
MBB
ODD/EVEN
MBA
FS1
FS0
PEFA
MBF2
ENA
CLKA
W/RA
VCC
PGA
AF
FF
CSA
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
NC
NC
3024 drw 02
TQFP (PN120-1, order code: PF)
TOP VIEW
Note:
1. NC = No internal connection
2
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
NC
NC
CSB
PGB
VCC
W/RB
CLKB
ENB
GND
PEFB
MBF1
GND
NC
NC
NC
NC
MBB
RST
MBA
FS1
FS0
ODD/EVEN
PEFA
GND
MBF2
*
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AE
EF
B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
VCC
A24
A25
A26
GND
A27
A28
A29
VCC
A30
A31
A32
GND
A33
A34
A35
GND
B35
B34
B33
GND
B32
B31
B30
VCC
B29
B28
B27
GND
B26
B25
B24
VCC
GND
NC
NC
A0
A1
A2
GND
A3
A4
A5
A6
VCC
A7
A8
A9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
AF
FF
CSA
ENA
CLKA
W/RA
VCC
PGA
PIN CONFIGURATION (CONTINUED)
3024 drw 03
PQFP (PQ132-1, order code: PQF)
TOP VIEW
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
3
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
A0-A35
Name
AE
Port-A Data
Almost-Empty Flag
AF
Almost-Full Flag.
B0-B35
CLKA
Port-B Data.
Port-A Clock
CLKB
Port-B Clock
CSA
Port-A Chip Select
CSB
Port-B Chip Select
EF
I/O
I/O 36-bit bidirectional data port for side B.
I CLKA is a continuous clock that synchronizes all data transfers through port-A
and can be aynchronous or coincident to CLKB. FF and AF are synchronized
to the LOW-to-HIGH transition of CLKA.
I CLKB is a continuous clock that synchronizes all data transfers through port-B
and can be asynchronous or coincident to CLKA. EF and AE are synchronized
to the LOW-to-HIGH transition of CLKB.
I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A. The A0-A35 outputs are in the high-impedance state
when CSA is HIGH.
I
O
ENA
Port-A Enable
I
ENB
Port-B Enable
I
Full Flag
O
Flag-Offset Selects
I
MBA
Port-A Mailbox Select
I
MBB
Port-B Mailbox Select
I
MBF1
Mail1 Register Flag
O
FS1, FS0
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B. The B0-B35 outputs are in the high-impedance state
when CSB is HIGH.
Empty Flag
FF
Description
I/O 36-bit bidirectional data port for side A.
O Programmable almost-empty flag synchronized to CLKB. It is LOW when
the number of words in the FIFO is less than or equal to the value in the offset
register, X.
O Programmable almost-full flag synchronized to CLKA. It is LOW when the
number of empty locations in the FIFO is less than or equal to the value in the
offset register, X.
EF is synchronized to the LOW-to-HIGH transition of CLKB.
When EF is LOW,
the FIFO is empty, and reads from its memory are disabled. Data can be read
from the FIFO to its output register when EF is HIGH. EF is forced LOW when
the device is reset and is set HIGH by the second LOW-to-HIGH transition of
CLKB after data is loaded into empty FIFO memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B.
FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW,
the FIFO is full, and writes to its memory are disabled. FF is forced LOW when
the device is reset and is set HIGH by the second LOW-to-HIGH transition of
CLKA after reset.
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1,
which loads one of four preset values into the almost-full and almost-empty
offset register (X).
A HIGH level on MBA chooses a mailbox register for a port-A read or write
operation.
A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the B0-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a LOW level selects the FIFO
output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set
LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B
read is selected and MBB is HIGH. MBF1 is set HIGH when the device is
reset.
4
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol
MBF2
Name
I/O
Mail2 Register Flag
O
Description
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while MBF2 is
LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a portA read is selected and MBA is HIGH. MBF2 is set HIGH when the device is
reset.
ODD/
EVEN
PEFA
PEFB
Odd/Even Parity
Select
Port-A Parity Error
Flag
Port-B Parity Error
Flag
PGA
Port-A Parity
Generation
PGB
Port-B Parity
Generation
RST
W/RA
W/RB
Reset
Port-A Write/Read
Select
Port-B Write/Read
Select
Odd parity is checked on each port when ODD/EVEN is HIGH, and even
parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW.
(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having CSA LOW, ENA HIGH, W/RA LOW, MBA
HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of
A0-A35 inputs.
O
When any byte applied to terminals B0-B35 fails parity, PEFB is LOW.
(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35, with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having CSB LOW, ENB HIGH, W/RB LOW,
MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the
state of the B0-B35 inputs
I
Parity is generated for mail2 register reads from port A when PGA is HIGH.
The type of parity generated is selected by the state of the ODD/EVEN input.
Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.
I
Parity is generated for data reads from port B when PGB is HIGH. The type
of parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-toHIGH transitions of CLKB must occur while RST is LOW. This sets the AF,
MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOWto-HIGH transition of RST latches the status of the FS1 and FS0 inputs to
select almost-full and almost-empty flag offset.
I
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
I
I
A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
5
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol
Rating
VCC
Unit
-0.5 to 7
V
Input Voltage Range
-0.5 to VCC+0.5
V
Output Voltage Range
-0.5 to VCC+0.5
V
Supply Voltage Range
(2)
VI
VO
Commercial
(2)
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
±20
mA
IOK
Output Clamp Current, (VO = < 0 or VO > VCC)
±50
mA
IOUT
Continuous Output Current, (VO = 0 to VCC)
±50
mA
ICC
Continuous Current Through VCC or GND
±500
mA
TA
Operating Free Air Temperature Range
0 to 70
°C
TSTG
Storage Temperature Range
-65 to 150
°C
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min. Max. Unit
VCC
Supply Voltage
4.5
5.5
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
0.8
V
IOH
High-Level Output Current
-4
mA
IOL
Low-Level Output Current
8
mA
TA
Operating Free-Air
Temperature
70
°C
2
V
V
0
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions
Min.
2.4
Typ.(1)
Max.
Unit
VOH
VCC = 4.5V,
IOH = -4 mA
VOL
VCC = 4.5 V,
IOL = 8 mA
0.5
V
ILI
VCC = 5.5 V,
VI = VCC or 0
±50
µA
ILO
VCC = 5.5 V,
VO = VCC or 0
±50
µA
ICC
VCC = 5.5 V,
IO = 0 mA,
Outputs HIGH
60
mA
Outputs LOW
130
Outputs Disabled
60
VI = VCC or GND
V
CIN
VI = 0,
f = 1 MHz
4
pF
COUT
VO = 0,
f = 1 MHZ
8
pF
Notes:
1. All typical values are at VCC = 5 V, TA = 25°C.
6
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURES
Symbol
IDT723611L15 IDT723611L20 IDT723611L30
Min. Max. Min. Max. Min. Max.
Parameter
Unit
fS
Clock Frequency, CLKA or CLKB
–
66.7
–
50
–
33.4
Mhz
tCLK
Clock Cycle Time, CLKA or CLKB
15
–
20
–
30
–
Mhz
tCLKH
Pulse Duration, CLKA or CLKB HIGH
6
–
8
–
12
–
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
6
–
8
–
12
–
ns
tDS
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
4
–
5
–
6
–
ns
tENS1
CSA, W/RA, before CLKA↑; CSB, W/RB before
CLKB↑
6
–
6
–
7
–
ns
tENS2
ENA before CLKA↑; ENB before CLKB↑
4
–
5
–
6
–
ns
tENS3
MBA before CLKA↑; ENB before CLKB↑
4
–
5
–
6
–
ns
tPGS
Setup Time, ODD/EVEN and PGB before
CLKB↑(1)
4
–
5
–
6
–
ns
tRSTS
Setup Time, RST LOW before CLKA↑
or CLKB↑(2)
5
–
6
–
7
–
ns
tFSS
Setup Time, FS0 and FS1 before RST HIGH
5
–
6
–
7
–
ns
1
–
1
–
1
–
ns
1
–
1
–
1
–
ns
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35
after CLKB↑
CSA, W/RA after CLKA↑; CSB, W/RB
tENH1
after CLKB↑
tENH2
ENA after CLKA↑; ENB after CLKB↑
1
1
1
ns
tENH3
MBA after CLKA↑; MBB after CLKB↑
1
1
1
ns
tPGH
Hold TIme, ODD/EVEN and PGB after CLKB↑(1)
0
–
0
–
0
–
ns
6
–
6
–
7
–
ns
4
–
4
–
4
–
ns
Skew Time, between CLKA↑ and CLKB↑
for EF, FF
8
–
8
–
10
–
ns
tSKEW2(3) Skew Time, between CLKA↑ and CLKB↑
for AE, AF
9
–
16
–
20
–
ns
Hold Time, RST LOW after CLKA↑ or CLKB↑
tRSTH
Hold Time, FS0 and FS1 after RST HIGH
tFSH
tSKEW1
(3)
(2)
Notes:
1. Only applies for a rising edge of CLKB that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
7
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
Symbol
Parameter
IDT723611L15 IDT723611L20 IDT723611L30
Min. Max. Min. Max. Min. Max.
fS
Clock Frequency, CLKA or CLKB
–
66.7
–
50
tA
Access Time, CLKB↑ to B0-B35
2
10
2
12
2
15
ns
tWFF
Propagation Delay Time, CLKA↑ to FF
2
10
2
12
2
15
ns
2
10
2
12
2
15
ns
2
10
2
12
2
15
ns
2
10
2
12
2
15
ns
1
9
1
12
1
15
ns
tREF
tPAE
tPAF
tPMF
Propagation Delay Time, CLKB↑ to EF
Propagation Delay Time, CLKB↑ to AE
Propagation Delay Time, CLKA↑ to AF
Propagation Delay Time, CLKA↑ to MBF1
LOW or MBF2 HIGH and CLKB↑ to MBF2
LOW or MBF1 HIGH
–
33.4
Unit
MHz
tPMR
Propagation Delay Time, CLKA↑ to B0-B35(1)
and CLKB↑ to A0-A35(2)
3
12
3
14
3
16
ns
tMDV
Propagation Delay Time, MBB to B0-B35 Valid
1
11
1
11.5
1
12
ns
tPDPE
Propagation Delay Time, A0-A35 Valid to PEFA
Valid; B0-B35 Valid to PEFB Valid
3
12
3
13
3
14
ns
3
11
3
12
3
14
ns
2
12
2
13
2
15
ns
1
12
1
13
1
15
ns
3
14
3
15
3
16
ns
1
15
1
20
1
30
ns
2
10
2
12
2
14
ns
1
9
1
10
1
11
ns
tPOPE
tPOPB(3)
tPEPE
tPEPB(3)
tRSF
tEN
tDIS
Propagation Delay Time, ODD/EVEN to PEFA
and PEFB
Propagation Delay Time, ODD/EVEN to Parity
Bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
Propagation Delay Time, CSA, ENA, W/RA,
MBA, or PGAto PEFA; CSB, ENB, W/RB,
MBB, or PGB to PEFB
Propagation Delay Time, CSA, ENA W/RA,
MBA, or PGA to Parity Bits (A8, A17, A26,
A35); CSB, ENB, W/RB, MBB, or PGB to Parity
Bits (B8, B17, B26, B35)
Propagation Delay Time, RST to AE LOW and
(AF, MBF1, MBF2) HIGH
Enable Time, CSA and W/RA LOW to A0-A35
Active and CSB LOW and W/RB HIGH to
B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35
at high impedance and CSB HIGH or W/RB
LOW to B0-B35 at high impedance
Notes:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
8
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTION
RESET (RST)
The IDT723611 is reset by taking the reset (RST) input
LOW for at least four port-A clock (CLKA) and four port-B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of the FIFO and forces the fullflag (FF) LOW, the empty flag (EF) LOW, the almost-empty
flag (AE) LOW, and the almost-full flag (AF) HIGH. A reset also
forces the mailbox flags (MBF1, MBF2) HIGH. After a reset,
FF is set HIGH after two LOW-to-HIGH transitions of CLKA.
Almost-Full and
Almost-Empty Flag
Offset Register (X)
FS1
FS0
RST
16
H
H
↑
12
H
L
↑
8
L
H
↑
4
L
L
↑
Table 1. Flag Programming
The device must be reset after power up before data is written
to its memory.
A LOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty offset register (X) with the value
selected by the flag select (FS0, FS1) inputs. The values that
can be loaded into the register are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled
by the port-A chip select (CSA) and the port-A write/read
select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35
outputs are active when both CSA and W/RA are LOW. Data
is loaded into the FIFO from the A0-A35 inputs on a LOW-toHIGH transition of CLKA when CSA is LOW, W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FF is HIGH (see Table 2).
The port-B control signals are identical to those of port A.
The state of the port-B data (B0-B35) outputs is controlled by
the port-B chip select (CSB) and the port-B write/read select
(W/RB). The B0-B35 outputs are in the high-impedance state
when either CSB or W/RB is HIGH. The B0-B35 outputs are
active when both CSB and W/RB are LOW. Data is read from
the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition
of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB
is LOW, and EF is HIGH (see Table 3).
CSA
W/RA
ENA
MBA
CLKA
A0-A35 Outputs
Port Functions
H
X
X
X
X
In High-Impedance State
None
L
H
L
X
X
In High-Impedance State
None
L
H
H
L
↑
In High-Impedance State
FIFO Write
L
H
H
H
↑
In High-Impedance State
Mail1 Write
L
L
L
L
X
Active, Mail2 Register
None
L
L
H
L
↑
Active, Mail2 Register
None
L
L
L
H
X
Active, Mail2 Register
None
L
L
H
H
↑
Active, Mail2 Register
Mail2 Read (set MBF2 HIGH)
Table 2. Port-A Enable Function Table
CSB
W/RB
ENB
MBB
CLKB
B0-B35 Outputs
Port Functions
H
X
X
X
X
In High-Impedance State
None
L
H
L
X
X
In High-Impedance State
None
L
H
H
L
↑
In High-Impedance State
None
L
H
H
H
↑
In High-Impedance State
Mail2 Write
L
L
L
L
X
Active, FIFO Output Register
None
L
L
H
L
↑
Active, FIFO Output Register
FIFO Read
L
L
L
H
X
Active, Mail1 Register
None
L
L
H
H
↑
Active, Mail1 Register
Mail1 Read (set MBF1 HIGH)
Table 3. Port-B Enable Function Table
9
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
The setup and hold-time constraints to the port clocks for
the port chip selects (CSA, CSB) and write/read selects (W/
RA, W/RB) are only for enabling write and read operations and
are not related to HIGH-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s
chip select and write/read select can change states during the
setup and hold-time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO flag is synchronized to its port clock through two
flip-flop stages. This is done to improve the flags’ reliability by
reducing the probability of mestastable events on their outputs
when CLKA and CLKB operate asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are
synchronized to CLKB. Table 4 shows the relationship to the
flags to the FIFO.
EMPTY FLAG (EF)
The FIFO empty flag is synchronized to the port clock that
reads data from its array (CLKB). When the empty flag is
HIGH, new data can be read to the FIFO output register.
When the empty flag is LOW, the FIFO is empty and attempted
FIFO reads are ignored.
The FIFO read pointer is incremented each time a new
word is clocked to its output register. The state machine that
controls an empty flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. A word written to the
FIFO can be read to the FIFO output register in a minimum of
three port-B clock (CLKB) cycles. Therefore, an empty flag is
LOW if a word in memory is the next data to be sent to the FIFO
output register and two CLKB cycles have not elapsed since
the time the word was written. The empty flag of the FIFO is
set HIGH by the second LOW-to-HIGH transition of CLKB,
and the new data word can be read to the FIFO output register
in the following cycle.
A LOW-to-HIGH transition on CLKB begins the first synchronized cycle of a write if the clock transition occurs at time
tSKEW1 or greater after the write. Otherwise, the subsequent
Number of Words
Synchronized
Synchronized
to CLKB
to CLKA
in the FIFO
EF
AE
AF
FF
0
L
L
H
H
1 to X
H
L
H
H
(X+1) to [64-(X+1)]
H
H
H
H
(64-X) to 63
H
H
L
H
64
H
H
L
L
Table 4. FIFO Flag Operation
Note:
X is the value in the almost-empty flag and almost-full
flag register.
CLKB cycle can be the first synchronization cycle (see figure
4).
FULL FLAG (FF)
The FIFO full flag is synchronized to the port clock that
writes data to its array (CLKA). When the full flag is HIGH, an
SRAM location is free to receive new data. No memory
locations are free when the full flag is LOW and attempted
writes to the FIFO are ignored.
Each time a word is written to the FIFO, its write pointer is
incremented. The state machine that controls the full flag
monitors a write pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from the FIFO, its previous
memory location is ready to be written in a minimum of three
port-A clock cycles. Therefore, a full flag is LOW if less than
two CLKA cycles have elapsed since the next memory write
location has been read. The second LOW-to-HIGH transition
on CLKA after the read sets the full flag HIGH and data can be
written in the following clock cycle.
A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see
figure 5).
ALMOST-EMPTY FLAG (AE)
The FIFO almost empty-flag is synchronized to the port
clock that reads data from its array (CLKB). The state
machine that controls the almost-empty flag monitors a write
pointer and read pointer comparator that indicates when the
FIFO SRAM status is almost empty, almost empty+1, or
almost empty+2. The almost-empty state is defined by the
value of the almost-full and almost-empty offset register (X).
This register is loaded with one of four preset values during a
device reset (see reset above). The almost-empty flag is LOW
when the FIFO contains X or less words in memory and is
HIGH when the FIFO contains (X+1) or more words.
Two LOW-to-HIGH transitions on the port-B clock (CLKB)
are required after a FIFO write for the almost-empty flag to
reflect the new level of fill. Therefore, the almost-empty flag
of a FIFO containing (X+1) or more words remains LOW if two
CLKB cycles have not elapsed since the write that filled the
memory to the (X+1) level. The almost-empty flag is set HIGH
by the second CLKB LOW-to-HIGH transition after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH
transition on CLKB begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the write that fills the
FIFO to (X+1) words. Otherwise, the subsequent CLKB cycle
can be the first synchronization cycle (see figure 6).
ALMOST FULL FLAG (AF)
The FIFO almost-full flag is synchronized to the port clock
that writes data to its array (CLKA). The state machine that
controls an almost-full flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almost10
IDT723611 CMOS SyncFIFO
64 x 36
empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset above).
The almost-full flag is LOW when the FIFO contains (64-X) or
more words in memory and is HIGH when the FIFO contains
[64-(X+1)] or less words.
Two LOW-to-HIGH transitions on the port-A clock (CLKA)
are required after a FIFO read for the almost-full flag to reflect
the new level of fill. Therefore, the almost-full flag of a FIFO
containing [64-(X+1)] or less words remains LOW if two CLKA
cycles have not elapsed since the read that reduced the
number of words in memory to [64-(X+1)]. The almost-full flag
is set HIGH by the second CLKA LOW-to-HIGH transition
after the FIFO read that reduces the number of words in
memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA
begins the first synchronization cycle if it occurs at time tSKEW2
or greater after the read that reduces the number of words in
memory to [64-(X+1)]. Otherwise, the subsequent CLKA
cycle can be the first synchronization cycle (see figure 7).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723611 to pass
command and control information between port A and port B.
The mailbox-select (MBA, MBB) inputs choose between a
mail register and a FIFO for a port data transfer operation. A
LOW-to-HIGH transition on CLKA writes A0-A35 data to the
mail1 register when port-A write is selected by CSA, W/RA,
and ENA with MBA HIGH. A LOW-to-HIGH transition on
CLKB writes B0-B35 data to the mail2 register when port-B
write is selected by CSB, W/RB, and ENB with MBB HIGH.
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while its mail flag is LOW.
When the port-B data (B0-B35) outputs are active, the data
on the bus comes from the FIFO output register when the portB mailbox select (MBB) input is LOW and from the mail1
register when MBB is HIGH. Mail2 data is always present on
the port-A data (A0-A35) outputs when they are active. The
mail1 register flag (MBF1) is set HIGH by a LOW-to-HIGH
transition on CLKB when a port-B read is selected by CSB, W/
RB, and ENB with MBB HIGH. The mail2 register flag (MBF2)
is set HIGH by a LOW-to-HIGH transition on CLKA when a
port-A read is selected by CSA, W/RA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.
PARITY CHECKING
The port-A (A0-A35) inputs and port-B (B0-B35) inputs
each have four parity trees to check the parity of incoming (or
outgoing) data. A parity failure on one or more bytes of the
input bus is reported by a LOW level on the port parity error flag
(PEFA, PEFB). Odd or even parity checking can be selected,
and the parity error flags can be ignored if this feature is not
desired.
Parity status is checked on each input bus according to the
level of the odd/even parity (ODD/EVEN) select input. A parity
error on one or more bytes of a port is reported by a LOW level
COMMERCIAL TEMPERATURE RANGES
on the corresponding port parity error flag (PEFA, PEFB)
output. Port-A bytes are arranged as A0-A8, A9-A17, A18A26, and A27-A35, and port-B bytes are arranged as B0-B8,
B9-B17, B18-B26, and B27-B35. When odd/even parity is
selected, a port parity error flag (PEFA, PEFB) is LOW if any
byte on the port has an odd/even number of LOW levels
applied to its bits.
The four parity trees used to check the A0-A35 inputs are
shared by the mail2 register when parity generation is selected for port-A reads (PGA=HIGH). When port-A read from
the mail2 register with parity generation is selected with CSA
LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH,
the port-A parity error flag (PEFA) is held HIGH regardless of
the levels applied to the A0-A35 inputs. Likewise, the parity
trees used to check the B0-B35 inputs are shared by the mail1
register when parity generation is selected for port-B reads
(PGB=HIGH). When a port-B read from the mail1 register with
parity generation is selected with CSB LOW, ENB HIGH, W/
RB LOW, MBB HIGH, and PGB HIGH, the port-B parity error
flag (PEFB) is held HIGH regardless of the levels applied to the
B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A parity generate select (PGA) or
port-B generate select (PGB) enables the IDT723611 to
generate parity bits for port reads from a FIFO or mailbox
register. Port-A bytes are arranged as A0-A8, A9-A17, A18A26, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as B0-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all thirty-six inputs regardless of the state of the parity generate select (PGA, PGB)
inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate
a parity bit according to the level on the ODD/EVEN select.
The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the
word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port-B parity generate select (PGB)
and ODD/EVEN have setup and hold time constraints to the
port-B clock (CLKB) for a rising edge of CLKB used to read a
new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port-B bus (B0-B35) to check parity and the
circuit used to generate parity for the mail2 data is shared by
the port-A bus (A0-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in
a mail register when the port write/read select (W/RA, W/RB)
input is LOW, the port mail select (MBA, MBB) input is HIGH,
chip select (CSA, CSB) is LOW, enable (ENA, ENB) is HIGH,
and the port parity generate select (PGA, PGB) is HIGH.
Generating parity for mail register data does not change the
contents of the register.
11
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKA
tRSTH
CLKB
tRSTS
tFSS
tFSH
RST
FS1,FS0
0,1
tWFF
tWFF
FF
tREF
EF
tPAE
AE
tPAF
AF
tRSF
MBF1,
MBF2
3024 drw 04
Figure 1. Device Reset Loading the X Register with the Value of Eight
tCLK
tCLKH
tCLKL
CLKA
FF
tENS1
tENH1
CSA
tENS1
tENH1
tENS3
tENH3
tENS2
tENH2
W/RA
MBA
tENS2
tENH2
tENS2
tENH2
ENA
tDH
tDS
A0 - A35
W1
No Operation
W2
ODD/
EVEN
PEFA
tPDPE
tPDPE
Valid
Valid
3024 drw 05
Figure 2. FIFO Write Cycle Timing
12
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
CLKB
EF
(HIGH)
CSB
W/RB
tENS2
MBB
tENH2
tENS2
tENH2
ENB
tMDV
tA
tEN
B0 - B35
No
Operation
tA
Previous Data
tPGH
tPGS
PGB,
ODD/
tENH2
tENS2
Word 1
tPGS
tDIS
Word 2
tPGH
EVEN
3024 drw 06
Figure 3. FIFO Read Cycle Timing
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
WR A
HIGH tENS3
tENH3
tENS2
tENH2
MBA
ENA
FFA
HIGH
A0 - A35
tDS
tDH
W1
tSKEW1(1)
CLKB
tCLK
tCLKH tCLKL
1
2
tREF
EF
tREF
Empty FIFO
CSB
LOW
W/RB
LOW
MBB
LOW
tENS2
tENH2
ENB
tA
B0 -B35
W1
3024 drw 07
Note:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Figure 4. EF Flag Timing and First Data Read when the FIFO is Empty
13
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
W/RB
LOW
MBB
LOW
tENH2
tENS2
ENB
EFB
B0 -B35
HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
tSKEW1(1)
tCLK
tCLKH
1
CLKA
FF
tCLKL
2
tWFF
tWFF
FIFO Full
CSA
LOW
WRA
HIGH
tENH3
tENS3
MBA
tENS2
tENH2
ENA
tDS
tDH
A0 - A35
To FIFO
3024 drw 08
Note:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Figure 5. FF Flag Timing and First Available Write when the FIFO is Full
CLKA
tENS2
tENH2
ENA
tSKEW2
(1)
1
CLKB
2
tPAE
tPAE
AE
X Word in FIFO
(X+1) Words in FIFO
tENS2
tENH2
ENB
3024 drw 09
Notes:
1. tSKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next
CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may
transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 6. Timing for AE when the FIFO is Almost Empty
14
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
tSKEW2
(1)
1
CLKA
2
tENH2
tENS2
ENA
tPAF
tPAF
AF
(64-X) Words in FIFO
[64-(X+1)] Words in FIFO
CLKB
tENS2
tENH2
ENB
3024 drw 10
Notes:
1. tSKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next
CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may
transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 7. Timing for AF when the FIFO is Almost Full
CLKA
tENS1
tENH1
CSA
W/RA
MBA
ENA
tDS
W1
A0 - A35
tDH
CLKB
tPMF
MBF1
tPMF
CSB
W/RB
MBB
tENS2
tENH2
ENB
tMDV
tEN
tDIS
tPMR
W1 (Remains valid in Mail1 Register after read)
B0 - B35
FIFO Output Register
Note:
1. Port-B parity generation off (PGB = L)
3024 drw 11
Figure 8. Timing for Mail1 Register and MBF1 Flag
15
IDT723611 CMOS SyncFIFO
64 x 36
CLKB
COMMERCIAL TEMPERATURE RANGES
tENH1
tENS1
CSB
W/RB
MBB
ENB
tDS
W1
B0 - B35
tDH
CLKA
tPMF
MBF2
tPMF
CSA
W/RA
MBA
tENS2
tENH2
ENA
tEN
tDIS
tPMR
W1 (Remains valid in Mail2 Register after read)
A0 - A35
3024 drw 12
Note:
1. Port-A parity generation off (PGA = L)
Figure 9. Timing for Mail2 Register and MBF2 Flag
ODD/
EVEN
W/RA
MBA
PGA
PEFA
Valid
tPEPE
tPOPE
tPOPE
Valid
Valid
tPEPE
Valid
3024 drw 13
Note:
1. CSA = L and ENA = H.
Figure 10. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
16
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
ODD/
EVEN
W/RB
MBB
PGB
tPOPE
PEFB
Valid
tPEPE
tPOPE
Valid
tPEPE
Valid
Valid
3024 drw 14
Note:
1. CSB = L and ENB = H.
Figure 11. ODD/EVEN, W/RB, MBB, and PGB to PEFB Timing
ODD/
EVEN
CSA
LOW
W/RA
MBA
PGA
tEN
A8, A17,
A26, A35
tPEPB
tPOPB
Generated Parity
Mail2 Data
tPEPB
Generated Parity
Mail2 Data
3024 drw 15
Note:
1. ENA = H.
Figure 12. Parity Generation Timing when reading from the Mail2 Register
ODD/
EVEN
CSB
LOW
W/RB
MBB
PGB
tEN
B8, B17,
B26, B35
tPEPB
tMDV
tPOPB
Generated Parity
tPEPB
Generated Parity
Mail1
Data
Mail1 Data
3024 drw 16
Note:
1. ENB = H.
Figure 13. Parity Generation Timing when reading from the Mail1 Register
17
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
VCC = 5.5 V
350
f data = 1/2 f s
T A = 25° C
C L = 0 pF
300
VCC = 5.0 V
I CC(f) – Supply Current – mA
250
VCC = 4.5 V
200
150
100
50
0
0
10
20
30
40
50
f clock – Clock Frequency – MHz
60
70
80
3024 drw 17
Figure 14.
CALCULATING POWER DISSIPATION
The ICC(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT723611 with
CLKA and CLKB operating at frequency fS. All data inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.
Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from FIgure 14, the maximum power dissipation (PT) of the IDT723611 may be calculated by:
PT = VCC x ICC(f) + ∑(CL x VOH - VOL)2 X fO)
where:
CL
=
fO
=
output capacitance load
switching frequency of an output
VOH
=
output high-level voltage
VOL
=
output low-level voltage
When no read or writes are occurring on the IDT723611, the power dissipated by a single clock (CLKA or CLKB) input
running at frequency fS is calculated by:
PT = VCC x fS x 0.290 mA/MHz
18
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k Ω
From Output
Under Test
30 pF
680 Ω
(1)
PROPAGATION DELAY
LOAD CIRCUIT
3V
Timing
Input
1.5 V
High-Level
Input
GND
tS
1.5 V
th
3V
1.5 V
1.5 V
GND
tW
3V
Data,
Enable
Input
Low-Level
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5 V
tPLZ
1.5 V
tPZL
GND
≈3 V
1.5 V
Low-Level
Output
Input
VOL
tPZH
VOH
High-Level
Output
3V
1.5 V
1.5 V
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
≈ OV
3V
1.5 V
1.5 V
tPD
tPD
GND
VOH
In-Phase
Output
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL
3024 drw 18
Note:
1. Includes probe and jig capacitance.
Figure 15. Load Circuit and Voltage Waveforms
19
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
BLANK Commercial (0°C to +70°C)
PF
PQF
15
20
30
L
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Low Power
723611 64 x 36 Synchronous FIFO
3024 drw 19
20
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