IDT IDT72V12165 3.3 volt multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16 Datasheet

3.3 VOLT MULTIMEDIA FIFO
256 x 16, 512 x 16,
1,024 x 16, 2,048 x 16,
and 4,096 x 16
IDT72V11165, IDT72V12165
IDT72V13165, IDT72V14165
IDT72V15165
FEATURES
DESCRIPTION
•
•
•
The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices
are First-In, First-Out (FIFO) memories with clocked read and write controls.
These FIFOs have 16-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is written
into the Multimedia FIFO on every clock when WEN is asserted. The output port
is controlled by another clock pin (RCLK) and another enable pin (REN). The
Read Clock (RCLK) can be tied to the Write Clock for single clock operation or
the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
These Multimedia FIFOs support three fixed flags: Empty Flag (EF), Full
Flag (FF), and Half Full Flag (HF).
•
•
•
•
•
•
•
•
•
256 x 16-bit organization array (IDT72V11165)
512 x 16-bit organization array (IDT72V12165)
1,024 x 16-bit organization array (IDT72V13165)
2,048 x 16-bit organization array (IDT72V14165)
4,096 x 16-bit organization array (IDT72V15165)
15 ns read/write cycle time
5V input tolerant
Independent Read and Write Clocks
Empty/Full and Half-Full flag capability
Output enable puts output data bus in high-impedance state
Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm
TQFP)
Industrial temperature range (–40°°C to +85°°C)
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
RCLK
READ
CONTROL
WRITE
CONTROL
REN
OE
FIFO ARRAY
D0 - D15
Data In
x16
Q0 - Q15
Data Out
x16
RESET LOGIC
FLAG OUTPUTS
EF
RS
HF
FF
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
NOVEMBER 2003
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6359/2
INDUSTRIAL
TEMPERATURE RANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
GND
D0
GND
RCLK
REN
VCC
OE
RS
VCC
GND
EF
Q0
DNC(1)
GND
Q1
VCC
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DNC(1)
GND
WCLK
WEN
GND
VCC
DNC(1)
VCC
FF
HF
DNC(1)
DNC(1)
Q15
GND
Q14
Q13
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PIN 1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q2
Q3
GND
Q4
Q5
VCC
Q6
Q7
GND
Q8
Q9
Q10
Q11
GND
Q12
VCC
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NOTE:
1. DNC = Do Not Connect.
STQFP (PP64-1, order code: TF)
TOP VIEW
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–D15
Data Inputs
I
Data inputs for an 16-bit bus.
EF
Empty Flag
O
EF indicates whether or not the FIFO memory is empty.
FF
Full Flag
O
FF indicates whether or not the FIFO memory is full.
HF
Half-Full Flag
O
The device is more than half full when HF is LOW.
OE
Output Enable
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
Q0–Q15
Data Outputs
O
Data outputs for an 16-bit bus.
RCLK
Read Clock
I
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
REN
Read Enable
I
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH,
the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW.
RS
Reset
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF
goes HIGH, and EF goes LOW. A reset is required before an initial WRITE after power-up.
WCLK
Write Clock
I
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
WEN
Write Enable
I
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
VCC
Power
I
+3.3V power supply pins.
GND
Ground
I
Ground pins.
2
INDUSTRIAL
TEMPERATURE RANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
ABSOLUTE MAXIMUM RATINGS
Symbol
(2)
Rating
Industrial
Unit
VTERM
Terminal Voltage
with respect to GND
–0.5 to +5
V
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output Current
–50 to +50
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
V
VCC
Supply Voltage Industrial
GND
Supply Voltage
VIH
Input High Voltage Industrial
2.0
—
5.5
V
Input Low Voltage Industrial
Operating Temperature
Industrial
-0.5
-40
—

0.8
85
V
°C
VIL
TA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminal only.
Parameter
(1)
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Symbol
ILI
(1)
Parameter
Min.
IDT72V11165
IDT72V12165
IDT72V13165
IDT72V14165
IDT72V15165
Industrial
tCLK = 15 ns
Typ.
Max.
Unit
Input Leakage Current (any input)
–1
—
1
µA
ILO(2)
Output Leakage Current
–10
—
10
µA
VOH
Output Logic “1” Voltage, IOH = –2 mA
2.4
—
—
V
VOL
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4
V
Active Power Supply Current
—
—
30
mA
Standby Current
—
—
5
mA
ICC1(3,4,5)
ICC2
(3,6)
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs disabled (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
5. Typical ICC1 = 2.04 + 0.88*fS + 0.02*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
(2)
Input
Capacitance
COUT(1,2)
Output
Capacitance
CIN
Max.
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3
INDUSTRIAL
TEMPERATURE RANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Industrial
IDT72V11165
IDT72V12165
IDT72V13165
IDT72V14165
IDT72V15165
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tHF
tSKEW1
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width(2)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(3)
Output Enable to Output Valid
Output Enable to Output in High-Z(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Half-Full Flag
Skew time between Read Clock & Write Clock for FF and EF
Min.
—
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
—
6
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
20
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for the 15ns speed grade available.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
510Ω
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
30pF*
6359 drw03
Figure 1. Output Load
* Includes jig and scope capacitances.
4
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURE RANGE
To prevent data overflow, FF will go LOW, inhibiting further write operations.
Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF flag is updated on the rising edge of WCLK.
FUNCTIONAL DESCRIPTION
WRITE/READ AND FLAG FUNCTION
To write data into to the FIFO, Write Enable (WEN) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full Flag (HF) would toggle to LOW once
the 129th (72V11165), 257th (72V12165), 513th (72V13165), 1,025th
(72V14165), and 2,049th (72V15165) word respectively was written into the
FIFO.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 256 writes for the IDT72V11165, 512 for the IDT72V12165,
1,024 for the IDT72V13165, 2,048 for the IDT72V14165 and 4,096 for the
IDT72V15165, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause the Half-Full Flag (HF) to go HIGH.
Continuing read operations will cause the FIFO to be empty. When the last word
has been read from the FIFO, the EF will go LOW inhibiting further read
operations. REN is ignored when the FIFO is empty.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the output
register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data and
no new data is loaded into the output register. The data outputs Q0-Qn maintain
the previous data value.
Every word accessed at Qn, including the first word written to an empty FIFO,
must be requested using REN. When the last word has been read from the FIFO,
the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is
ignored when the FIFO is empty. Once a write is performed, EF will go HIGH
allowing a read to occur. The EF flag is updated on the rising edge of RCLK.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When OE is disabled (HIGH), the Q output
data bus is in a high-impedance state.
SIGNAL DESCRIPTIONS
INPUTS
DATA IN (D0 - D15)
Data inputs for 16-bit wide data.
OUTPUTS
FULL FLAG/INPUT READY (FF)
When the FIFO is full, FF will go LOW, inhibiting further write operations.
When FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72V11165,
512 for the IDT72V12165, 1,024 for the IDT72V13165, 2,048 for the
IDT72V14165 and 4,096 for the IDT72V15165.
FF is synchronous and updated on the rising edge of WCLK.
CONTROLS
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Half-Full Flag (HF) to HIGH after tRSF. The Full Flag (FF) will reset
to HIGH. The Empty Flag (EF) will reset to LOW. During reset, the output register
is initialized to all zeros and the offset registers are initialized to their default values.
EMPTY FLAG/OUTPUT READY (EF)
When the FIFO is empty, EF will go LOW, inhibiting further read operations.
When EF is HIGH, the FIFO is not empty.
EF is synchronous and updated on the rising edge of RCLK.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met with respect to the LOW-to-HIGH
transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
HALF-FULL FLAG (HF)
After half of the memory is filled, and at the LOW-to-HIGH transition of the next
write cycle, the Half-Full Flag goes LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is
asynchronous.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
DATA OUTPUTS (Q0-Q15)
Data outputs for 16-bit wide data.
5
INDUSTRIAL
TEMPERATURE RANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
tRS
RS
tRSR
REN, WEN
RCLK, WCLK
(1)
tRSF
IDT Standard Mode
FF
tRSF
EF
IDT Standard Mode
tRSF
HF
tRSF
(2)
OE = 1
Q0 - Q15
OE = 0
6359 drw04
NOTES:
1. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
2. After reset, the outputs will be LOW if OE = 0 and high-impedanced if OE = 1.
Figure 2. Reset Timing(1)
NO WRITE
NO WRITE
WCLK
1
2
1
tDS
(1)
tSKEW1
2
(1)
tSKEW1
D0 - D15
DATA WRITE
tDS
Wd
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
OE LOW
tA
tA
Q0 - Q15
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
6359 drw24
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
Figure 3. Full Flag Timing
6
INDUSTRIAL
TEMPERATURE RANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
tCLK
tCLKH
tCLKL
1
WCLK
2
tDS
tDH
D0 - D15
DATA IN VALID
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1(1)
RCLK
REN
6359 drw25
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.
Figure 4. Write Cycle Timing
tCLKH
1
RCLK
tCLK
tCLKL
2
tENH
tENS
REN
NO OPERATION
tREF
tREF
EF
tA
Q0 - Q15
LAST WORD
tOLZ
tOHZ
tOE
OE
(1)
tSKEW1
WCLK
tENS
tENH
WEN
tDS
D0 - D15
tDH
FIRST WORD
6359 drw26
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
Figure 5. Read Cycle Timing
7
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
I
Industrial (-40°C to +85°C)
TF
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
15
Industrial
L
Low Power
72V11165
72V12165
72V13165
72V14165
72V15165
256 x 16
512 x 16
1,024 x 16
2,048 x 16
4,096 x 16
Clock Cycle Time (tCLK)
Speed in Nanoseconds





3.3V Multimedia FIFO
3.3V Multimedia FIFO
3.3V Multimedia FIFO
3.3V Multimedia FIFO
3.3V Multimedia FIFO
6359 drw32
DATASHEET DOCUMENT HISTORY
11/17/2003
pg. 1.
CORPORATE HEADQUARTERS
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8
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(408) 330-1753
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