IDT IDT74FCT16373CTE Fast cmos 16-bit transparent latch Datasheet

FAST CMOS 16-BIT
TRANSPARENT
LATCHES
IDT54/74FCT16373T/AT/CT/ET
IDT54/74FCT162373T/AT/CT/ET
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16373T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162373T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
The FCT16373T/AT/CT/ET and FCT162373T/AT/CT/ET
16-bit transparent D-type latches are built using advanced
dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be
used for implementing memory address latches, I/O ports,
and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 8-bit latches, or
one 16-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16373T/AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162373T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times– reducing the need for external series terminating resistors. The
FCT162373T/AT/CT/ET are plug-in replacements for the
FCT16373T/AT/CT/ET and ABT16373 for on-board interface
applications.
FUNCTIONAL BLOCK DIAGRAM
1OE
2OE
1LE
2LE
1D1
2D1
D
D
1O1
2O1
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2543 drw 02
2543 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
5.7
AUGUST 1996
DSC-4229/9
1
IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1OE
1
48
1LE
1OE
1
48
1LE
1O1
2
47
1D1
1O1
2
47
1D1
1O2
3
46
1D2
1O2
3
46
1D2
GND
4
45
GND
GND
4
45
GND
1O3
5
44
1D3
1O3
5
44
1D3
1O4
6
43
1D4
1O4
6
43
1D4
VCC
7
42
VCC
VCC
7
42
VCC
1O5
8
41
1D5
1O5
8
41
1D5
1O6
9
40
1D6
1O6
9
40
1D6
GND
10
39
GND
GND
10
39
GND
1O7
11
38
1D7
1O7
11
38
1D7
1O8
37
1D8
1O8
12
37
1D8
2O1
12 SO48-1
SO48-2
13 SO48-3
36
2D1
2O1
13
36
2D1
2O2
14
35
2D2
2O2
14
35
2D2
GND
15
34
GND
GND
15
34
GND
2O3
16
33
2D3
2O3
16
33
2D3
2O4
17
32
2D4
2O4
17
32
2D4
VCC
18
31
VCC
VCC
18
31
VCC
2O5
19
30
2D5
2O5
19
30
2D5
2O6
20
29
2D6
2O6
20
29
2D6
GND
21
28
GND
GND
21
28
GND
2O7
22
27
2D7
2O7
22
27
2D7
2O8
23
26
2D8
2O8
23
26
2D8
2OE
24
25
2LE
2OE
24
25
2LE
E48-1
2543 drw 03
2543 drw 04
SSOP/
TSSOP/TVSOP
TOP VIEW
CERPACK
TOP VIEW
5.7
2
IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
xDx
Description
Data Inputs
Inputs
xLE
xOE
Outputs
xOx
H
H
L
H
xLE
Latch Enable Input (Active HIGH)
xOE
Output Enable Input (Active LOW)
L
H
L
L
xOx
3-State Outputs
X
X
H
Z
2543 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
VTERM(3) Terminal Voltage with Respect to
–0.5 to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
I OUT
xDx
DC Output Current
–60 to +120
NOTE:
1. H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High-impedance
2543 tbl 02
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Unit
V
V
°C
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
Max. Unit
6.0
pF
8.0
pF
2543 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
mA
2543 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.7
3
IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current (Input pins)(5)
Symbol
VIH
Min.
2.0
Typ.(2)
—
Max.
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
—
—
±1
—
—
±1
—
—
±1
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
II L
Input LOW Current (Input
pins)(5)
VI = GND
Input LOW Current (I/O pins)(5)
I OZH
High Impedance Output Current
VCC = Max.
VO = 2.7V
pins) (5)
I OZL
(3-State Output
VIK
Clamp Diode Voltage
I OS
Short Circuit Current
VH
Input Hysteresis
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = 0.5V
VCC = Min., IIN = –18mA
VCC = Max., VO =
GND (3)
—
VCC = Max., VIN = GND or VCC
—
Unit
V
µA
—
—
±1
—
–0.7
–1.2
V
–80
–140
–225
mA
—
100
—
mV
—
5
500
µA
2543 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16373T
Symbol
IO
Parameter
Output Drive Current
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min.
–50
Typ.(2)
Max.
—
–180
Unit
mA
VOH
Output HIGH Voltage
VCC = Min.
2.5
3.5
—
V
2.4
3.5
—
V
2.0
3.0
—
V
—
0.2
0.55
V
—
—
±1
I OH = –3mA
VIN = VIH or V IL
VOL
Output LOW Voltage
I OFF
Input/Output Power Off Leakage(5)
VCC = Min.
VIN = VIH or V IL
VCC = 0V, VIN or V O
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OH = –24mA MIL.
I OH = –32mA COM'L.(4)
I OL = 48mA MIL.
I OL = 64mA COM'L.
≤ 4.5V
µA
2543 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162373T
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
60
Typ.(2)
115
Max.
200
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–60
–115
–200
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or V IL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.55
V
I OH = –16mA MIL.
I OH = –24mA COM'L.
I OL = 16mA MIL.
I OL = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.7
2543 lnk 07
4
IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Symbol
Parameter
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current (6)
VCC = Max.
Outputs Open
fi =10MHz
50% Duty Cycle
xOE = GND
xLE = VCC
One Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE = GND
xLE = VCC
Sixteen Bits Toggling
Min.
Typ.(2)
Max.
Unit
—
0.5
1.5
mA
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
VIN = VCC
VIN = GND
—
0.6
1.5
mA
VIN = 3.4V
VIN = GND
—
0.9
2.3
VIN = VCC
VIN = GND
—
2.4
4.5 (5)
VIN = 3.4V
VIN = GND
—
6.4
16.5 (5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.7
2543 tbl 08
5
IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16373T/162373T
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
FCT16373AT/162373AT
Mil.
Com'l.
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
CL = 50pF
RL = 500Ω
1.5
8.0
1.5
8.5
1.5
5.2
1.5
5.6
ns
2.0
13.0
2.0
15.0
2.0
8.5
2.0
9.8
ns
1.5
12.0
1.5
13.5
1.5
6.5
1.5
7.5
ns
Output Disable Time
1.5
7.5
1.5
10.0
1.5
5.5
1.5
6.5
ns
Set-up Time HIGH or LOW,
xDx to xLE
Hold Time HIGH or LOW,
xDx to xLE
xLE Pulse Width HIGH
2.0
—
2.0
—
2.0
—
2.0
—
ns
1.5
—
1.5
—
1.5
—
1.5
—
ns
6.0
—
6.0
—
5.0
—
6.0
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
ns
tSK(o) Output Skew (3)
FCT16373CT/162373CT
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
Mil.
Parameter
Parameter
Condition(1)
Min.(2)
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
CL = 50pF
RL = 500Ω
1.5
Mil.
Max.
Min.(2)
4.2
1.5
2.0
5.5
1.5
Output Disable Time
Set-up Time HIGH or LOW,
xDx to xLE
Hold Time HIGH or LOW,
xDx to xLE
xLE Pulse Width HIGH
tSK(o) Output Skew (3)
FCT16373ET/162373ET
Com'l.
Mil.
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
5.1
1.5
3.4
—
—
ns
2.0
8.0
1.5
3.7
—
—
ns
5.5
1.5
6.3
1.5
4.4
—
—
ns
1.5
5.0
1.5
5.9
1.5
3.6
—
—
ns
2.0
—
2.0
—
1.0
—
—
—
ns
1.5
—
1.5
—
1.0
—
—
—
ns
5.0
—
6.0
—
3.0 (4)
—
—
—
ns
—
0.5
—
0.5
—
0.5
—
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5.7
2543 tbl 09
6
IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
500Ω
VIN
Open Drain
Disable Low
Closed
Open
All Other Tests
D.U.T.
50pF
RT
Switch
Enable Low
V OUT
Pulse
Generator
Test
2543 lnk 10
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2543 drw 05
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2543 drw 07
3V
1.5V
0V
tH
2543 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
CONTROL
INPUT
tPZL
VOH
1.5V
VOL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
2543 drw 08
SWITCH
OPEN
0V
tPLZ
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2543 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.7
7
IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
Temp. Range
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
CERPACK (E48-1)
16373T
Non-Inverting 16-Bit Transparent Latch
16373AT
16373CT
16373ET
162373T
162373AT
162373CT
162373ET
54
74
–55°C to +125°C
–40°C to +85°C
2543 drw 10
5.7
8
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