IDT IDT74FCT2648DTDB Fast cmos octal transceiver/ registers (3-state) Datasheet

FAST CMOS OCTAL
TRANSCEIVER/
REGISTERS (3-STATE)
IDT54/74FCT646T/AT/CT/DT - 2646T/AT/CT
IDT54/74FCT648T/AT/CT
IDT54/74FCT652T/AT/CT/DT - 2652T/AT/CT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
– Low input and output leakage ≤1µA (max.)
– Extended commercial range of –40°C to +85°C
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, TSSOP,
CERPACK and LCC packages
• Features for FCT646T/648T/652T:
– Std., A, C and D speed grades
– High drive outputs (-15mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
• Features for FCT2646T/2652T:
– Std., A, and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
– Reduced system switching noise
The FCT646T/FCT2646T/FCT648T/FCT652T/2652T consist of a bus transceiver with 3-state D-type flip-flops and
control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage registers.
The FCT652T/FCT2652T utilize GAB and GBA signals to
control the transceiver functions. The FCT646T/FCT2646T/
FCT648T utilize the enable control (G) and direction (DIR)
pins to control the transceiver functions.
SAB and SBA control pins are provided to select either realtime or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and realtime data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or
enable control pins.
The FCT26xxT have balanced drive outputs with current
limiting resistors. This offers low ground bounce, minimal
undershoot and controlled output fall times-reducing the need
for external series terminating resistors. FCT2xxxT parts are
plug-in replacements for FCTxxxT parts.
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT652/2652
ONLY
GAB
GBA
IDT54/74FCT646/2646/648
ONLY
G
DIR
CPBA
SBA
CPAB
SAB
B REG
1 OF 8 CHANNELS
A1
1D
C1
A REG
1D
646/2646/652/2652
ONLY
B1
C1
646/2646/652/2652
ONLY
2634 drw 01
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
6.20
SEPTEMBER 1996
DSC-2634/9
1
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
5
A2
A3
6
7
NC
A4
8
A5
A6
CPBA
SBA
4
3 2 1 28 27 26
25
G
24
B1
23
B2
22
21
NC
B3
L28-1
9
10
20
1112 13 14 15 16 17 1819
2634 drw 02
DIP/SOIC/SSOP/
QSOP/TSSOP/CERPACK
TOP VIEW
B4
B5
B6
B1
B2
B3
B4
B5
B6
B7
B8
A1
B7
G
FCT646/FCT2646T
FCT648
SAB
VCC
CPBA
SBA
GND
NC
B8
P24-1
D24-1
SO24-2
SO24-7*
SO24-8
SO24-9*
&
E24-1
24
23
22
21
20
19
18
17
16
15
14
13
DIR
1
2
3
4
5
6
7
8
9
10
11
12
A7
CPAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
INDEX
A8
PIN CONFIGURATIONS
CPAB
NC
VCC
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2634 drw 03
LCC
TOP VIEW
FCT652/FCT2652T
A1
5
A2
A3
6
7
A6
23
L28-1
8
22
21
9
10
20
19
11
12 13 14 15 16 17 18
2634 drw 04
DIP/SOIC/SSOP/
QSOP/CERPACK
TOP VIEW
GBA
B1
B2
NC
B3
B4
B5
B6
A4
A5
3 2 1 28 27 26
25
24
B7
NC
4
B8
B1
B2
B3
B4
B5
B6
B7
B8
GND
NC
GBA
CPBA
SBA
INDEX
SAB
VCC
CPBA
SBA
A8
P24-1
D24-1
SO24-2
SO24-7*
SO24-8
&
E24-1
24
23
22
21
20
19
18
17
16
15
14
13
GAB
1
2
3
4
5
6
7
8
9
10
11
12
A7
CPAB
SAB
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
CPAB
NC
VCC
* FCT646/2646T/AT/CT/DT only
2634 drw 05
LCC
TOP VIEW
* FCT652/2652T/AT/CT/DT only
PIN DESCRIPTION
Pin Names
A1 - A 8
B1 - B 8
CPAB, CPBA
SAB, SBA
DIR, G
GAB, GBA
Description
Data Register A Inputs
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs (646/648)
Output Enable Inputs (652)
2634 tbl 01
6.20
2
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (646/648)
Data I/O(1)
Inputs
Operation or Function
G
DIR
CPAB
CPBA
SAB
SBA
A1 - A8
B1 - B8
H
H
X
X
H or L
↑
H or L
↑
X
X
X
X
Input
Input
Isolation
Store A and B Data
Isolation
Store A and B Data
L
L
L
L
L
L
H
H
X
X
X
H or L
X
H or L
X
X
X
X
L
H
L
H
X
X
Output
Input
Input
Output
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
FCT646T/FCT2646T
FCT648T
2634 tbl 02
FUNCTION TABLE (652)
Inputs
Data I/O
Operation or Function
GAB
GBA
CPAB
CPBA
SAB
SBA
A1 - A8
B1 - B8
L
L
H
H
H or L
↑
H or L
↑
X
X
X
X
Input
Input
X
H
H
H
↑
↑
H or L
↑
X
X(2)
X
X
Input
Input
L
L
X
L
H or L
↑
↑
↑
X
X
X
X(2)
Unspecified(1)
Output
Input
Input
Hold A, Store B
Store B in Both Registers
L
L
H
H
H
L
L
H
H
L
X
X
X
H or L
H or L
X
H or L
X
X
H or L
X
X
L
H
H
L
H
X
X
H
Output
Input
Input
Output
Output
Output
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and Stored B Data to A Bus
FCT652T/FCT2652T
Isolation
Store A and B Data
Unspecified(1) Store A, Hold B
Output
Store A in Both Registers
NOTES:
1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
H = HIGH, L = LOW, X = Don't Care, ≠ = LOW-to-HIGH transition.
3. A in B Register.
4. B in A Register.
6.20
2634 tbl 03
3
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
BUS
A
GAB
L
646/2646/ DIR
648
L
652/2652
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
GBA
L
G
L
CPAB
X
CPAB
X
CPBA
X
CPBA
X
SAB
X
SAB
X
SBA
L
SBA
L
BUS
B
652/2652
GAB
H
GBA
H
CPAB
X
CPBA
X
SAB
L
SBA
X
646/2646/
648
DIR
H
G
L
CPAB
X
CPBA
X
SAB
L
SBA
X
REAL-TIME TRANSFER
BUS B TO A
REAL-TIME TRANSFER
BUS A TO B
2634 drw 06
BUS
A
652/2652
646/2646/
648
2634 drw 07
BUS
A
BUS
B
GAB
X
L
L
GBA
H
X
H
CPAB
↑
X
DIR
H
L
X
G
L
L
H
CPAB
↑
X
↑
↑
STORAGE FROM
A AND/OR B
CPBA
X
↑
↑
CPBA
X
↑
↑
SAB
X
X
X
SBA
X
X
X
SAB
X
X
X
SBA
X
X
X
652/2652
GAB
H
BUS
B
GBA
L
CPAB
H or
CPBA
H or
SAB
H
SBA
H
G
L
L
CPAB
X
H or
CPBA
H or
X
SAB
X
H
SBA
H
X
(1)
646/2646/
648
DIR
L
H
TRANSFER STORES
DATA TO A AND/OR B
2634 drw 09
NOTE:
1. 646/2646/648 cannot transfer data to A bus and B bus simultaneously.
2634 drw 08
6.20
4
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
(3)
VTERM
Terminal Voltage with Respect to
–0.5 to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
Unit
V
I OUT
mA
DC Output Current
–60 to +120
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
V
Conditions
VIN = 0V
Typ.
6
VOUT = 0V
8
Max. Unit
10
pF
12
NOTE:
1. This parameter is measured at characterization but not tested.
°C
pF
2634 lnk 05
2634 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Input LOW Level
Current(4)
II H
Input HIGH
II L
Input LOW Current (4)
I OZH
High Impedance Output Current
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
VI = 2.7V
—
—
±1
µA
VI = 0.5V
—
—
±1
VO = 2.7V
—
—
±1
VCC = Max.
µA
I OZL
(3-State Output
—
—
±1
II
Input HIGH Current(4)
VCC = Max., VI = VCC (Max.)
—
—
±1
µA
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
VH
Input Hysteresis
—
—
200
—
mV
I CC
Quiescent Power Supply Current
—
0.01
1
mA
pins) (4)
VO = 0.5V
VCC = Max., VIN = GND or VCC
2634 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT646T/648T/652T
VOL
Output LOW Voltage
I OS
Short Circuit Current
Test Conditions(1)
VCC = Min.
I OH = –6mA MIL.
VIN = VIH or V IL
I OH = –8mA COM'L.
I OH = –12mA MIL.
I OH = –15mA COM'L.
VCC = Min.
I OL = 48mA MIL.
VIN = VIH or V IL
I OL = 64mA COM'L.
VCC = Max., VO = GND (3)
I OFF
Input/Output Power Off Leakage(5)
VCC = 0V, VIN or V O ≤ 4.5V
Symbol
VOH
Parameter
Output HIGH Voltage
Min.
2.4
Typ.(2)
3.3
Max.
—
Unit
V
2.0
3.0
—
V
—
0.3
0.55
V
–60
–120
–225
mA
—
—
±1
µA
2634 lnk 06
6.20
5
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUT DRIVE CHARACTERISTICS FOR FCT2646T/2652T
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
16
Typ.(2)
48
Max.
—
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3)
–16
–48
—
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.50
V
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OL = 12mA
2634 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
ICCD
IC
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current (4)
Total Power Supply Current (6)
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
GAB = GBA = GND or
G = DIR = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
GAB = GBA = GND or
G = DIR = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
GAB = GBA = GND or
G = DIR = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
—
Typ.(2)
0.5
Max.
2.0
Unit
mA
—
0.15
0.25
mA/
MHz
FCT2xxxT
—
0.06
0.12
VIN = VCC FCTxxxT
VIN = GND
FCT2xxxT
—
1.5
3.5
—
0.6
2.2
FCTxxxT
VIN = 3.4
VIN = GND
FCT2xxxT
—
2.0
5.5
1.1
4.2
VIN = VCC FCTxxxT
VIN = GND
FCT2xxxT
—
3.8
7.3 (5)
—
1.5
4.0 (5)
—
6.0
16.3 (5)
—
3.8
13.0 (5)
VIN = VCC FCTxxxT
VIN = GND
VIN = 3.4
FCTxxxT
VIN = GND
FCT2xxxT
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.20
mA
2634 tbl 08
6
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
646/648/652T
2646/2652T
Com'l.
Mil.
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
Parameter
Propagation Delay
Bus to Bus
Output Enable Time, G,
DIR to Bus (3)
Output Disable Time, G,
DIR to Bus (3)
Propagation Delay
Clock to Bus
Propagation Delay SBA or
SAB to Bus
Set-up Time HIGH or LOW
Bus to Clock
Hold Time HIGH or LOW
Bus to Clock
Clock Pulse Width,
HIGH or LOW
Condition(1)
CL = 50pF
RL = 500Ω
646/648/652AT
2646/2652AT
Com'l.
Mil.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
Unit
ns
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
ns
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
ns
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
ns
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
ns
4.0
—
4.5
—
2.0
—
2.0
—
ns
2.0
—
2.0
—
1.5
—
1.5
—
ns
6.0
—
6.0
—
5.0
—
5.0
—
ns
2634 tbl 09
646/648/652CT
2646/2652CT
Com'l.
Mil.
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
Parameter
Propagation Delay
Bus to Bus
Output Enable Time, G,
DIR to Bus (3)
Output Disable Time, G,
DIR to Bus (3)
Propagation Delay
Clock to Bus
Propagation Delay SBA or
SAB to Bus
Set-up Time HIGH or LOW
Bus to Clock
Hold Time HIGH or LOW
Bus to Clock
Clock Pulse Width,
HIGH or LOW(4)
Condition(1)
CL = 50pF
RL = 500Ω
646/652DT
Com'l.
Mil.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
1.5
5.4
1.5
6.0
1.5
4.4
—
—
Unit
ns
1.5
7.8
1.5
8.9
1.5
5.0
—
—
ns
1.5
6.3
1.5
7.7
1.5
4.3
—
—
ns
1.5
5.7
1.5
6.3
1.5
4.4
—
—
ns
1.5
6.2
1.5
7.0
1.5
5.0
—
—
ns
2.0
—
2.0
—
1.5
—
—
—
ns
1.5
—
1.5
—
1.0
—
—
—
ns
5.0
—
5.0
—
3.0
—
—
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. GAB, GBA to Bus for 652.
4. This parameter is guaranteed but not tested.
2634 tbl 10
6.20
7
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
500Ω
Pulse
Generator
Switch
Open Drain
Disable Low
Closed
Enable Low
V OUT
VIN
Test
Open
All Other Tests
D.U.T.
50pF
RT
2634 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2634 drw 10
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2634 drw 12
3V
1.5V
0V
tH
2634 drw 11
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
2634 drw 13
SWITCH
OPEN
3.5V
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
0V
tPLZ
tPZL
VOH
1.5V
VOL
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2634 drw 14
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.20
8
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
X
Temperature
Family
Range
XXXX
Device Type
X
Package
X
Process/
Temperature
Range
Blank
B
Commercial
MIL-STD-883, Class B
P
D
SO
L
E
PY
Q
PG
Plastic DIP (P24-1)
CERDIP (D24-1)
Small Outline IC (SO24-2)
Leadless Chip Carrier (L28-1)
CERPACK (E24-1)
Shrink Small Outline Package (SO24-7)
Quarter-size Small Outline Package (SO24-8)
Thin Shrink Small Outline Package (SO24-9)
646T
648T
652T
646AT
648AT
652AT
646CT
648CT
652CT
646DT
652DT
Non-inverting Octal Transceiver/Register
Inverting Octal Transceiver/Register
Inverting Octal Transceiver/Register
Non-inverting Octal Transceiver/Register
Blank
2
High Drive
Balanced Drive
54
74
–55°C to +125°C
–40°C to +85°C
2634 drw 15
6.20
9
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