IDT IDT74FCT543DTQ Fast cmos octal latched transceiver Datasheet

IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
IDT74FCT543AT/CT/DT
FEATURES:
DESCRIPTION:
•
•
•
•
The FCT543T is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. This device contains two sets of eight D-type
latches with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must be low in order
to enter data from A0–A7 or to take data from B0–B7, as indicated in the
Function Table. With CEAB low, a low signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent low-tohigh transition of the LEAB signal puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB and OEAB both
low, the 3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
•
•
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A, C, and D grades
Low input and output leakage ≤1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
High Drive outputs (-15mA IOH, 64mA IOL)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC and QSOP packages
FUNCTIONAL BLOCK DIAGRAM
DETAIL A
D
Q
B0
LE
Q
A0
D
LE
A1
B1
A2
B2
A3
A4
B3
DETAIL A x 7
B4
A5
B5
A6
B6
A7
B7
OEBA
OEAB
CEBA
LEBA
CEAB
LEAB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-5489/6
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
LEBA
1
ABSOLUTE MAXIMUM RATINGS(1)
24
VCC
OEBA
2
23
CEBA
A0
3
22
B0
A1
4
21
B1
A2
5
20
B2
A3
6
19
B3
A4
7
18
B4
A5
8
17
B5
A6
9
16
B6
A7
10
15
B7
CEAB
11
14
LEAB
GND
12
13
OEAB
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0–A7
B0–B7
2
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1, 2)
For A-to-B (Symmetric with B-to-A)
CEAB
H
X
X
L
L
Inputs
LEAB
X
H
X
L
H
OEAB
X
X
H
L
L
Latch
Status
A-to-B
Storing
Storing
X
Transparent
Storing
Output
Buffers
B0–B7
High Z
X
High Z
Current A Inputs
Previous* A Inputs
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA
and OEBA.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
—
—
±1
µA
IIL
Input LOW Current(4)
VCC = Max.
VI = 0.5V
—
—
±1
µA
IOZH
High Impedance Output Current
VCC = Max
VO = 2.7V
—
—
±1
µA
IOZL
(3-State output pins)(4)
II
VIK
VH
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max., VI = VCC (Max.)
VCC = Min, IIN = -18mA
ICC
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
VO = 0.5V
—
—
—
±1
—
—
—
—
–0.7
200
±1
–1.2
—
µA
V
mV
—
0.01
1
mA
Min.
2.4
Typ.(2)
3.3
Max.
—
Unit
V
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Parameter
Output HIGH Voltage
VCC = Min
Test Conditions(1)
IOH = –8mA
VIN = VIH or VIL
IOH = –15mA
2
3
—
IOL = 64mA
—
0.3
0.55
V
–60
–120
–225
mA
—
—
±1
µA
VOL
Output LOW Voltage
IOS
Short Circuit Current
VCC = Min
VIN = VIH or VIL
VCC = Max., VO = GND(3)
IOFF
Input/Output Power Off Leakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
3
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Symbol
Parameter
ΔICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max., Outputs Open
CEAB and OEAB = GND
CEBA = VCC
One Input Toggling
50% Duty Cycle
Total Power Supply Current(6)
VCC = Max., Outputs Open
fCP = 10MHz (LEAB )
50% Duty Cycle
CEAB and OEAB = GND
CEBA = VCC
One Bit Toggling
at fi = 5MHz
50% duty cycle
VCC = Max., Outputs Open
fCP = 10MHz (LEAB )
50% Duty Cycle
CEAB and OEAB = GND
CEBA = VCC
Eight Bits Toggling
at fi = 2.5MHz
50% duty cycle
IC
Min.
Typ.(2)
Max.
Unit
—
0.5
2
mA
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
VIN = VCC
VIN = GND
—
1.5
3.5
mA
VIN = 3.4V
VIN = GND
—
2
5.5
VIN = VCC
VIN = GND
—
3.8
7.3(5)
VIN = 3.4V
VIN = GND
—
6
16.3(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
mA
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
74FCT543AT
Symbol
Parameter
74FCT543CT
74FCT543DT
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
6.5
1.5
5.3
1.5
4.4
ns
1.5
8
1.5
7
1.5
5
ns
1.5
9
1.5
8
1.5
5.4
ns
1.5
7.5
1.5
6.5
1.5
4.3
ns
2
—
2
—
1.5
—
ns
2
—
2
—
1.5
—
ns
5
—
5
—
3(3)
—
ns
tPLH
Propagation Delay
CL = 50pF
tPHL
Transparant Mode
RL = 500Ω
Ax to Bx or Bx to Ax
tPLH
Propagation Delay
tPHL
LEBA to Ax, LEAB to Bx
tPZH
Output Enable Time
tPZL
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
tPHZ
Output Disable Time
tPLZ
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
tSU
Set-up Time, HIGH or LOW
Ax or Bx to LEBA or LEAB
tH
Hold Time, HIGH or LOW
Ax or Bx to LEBA or LEAB
tW
LEBA or LEAB Pulse Width LOW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
5
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
SWITCH POSITION
7.0V
500W
V OUT
VIN
Pulse
Generator
D.U.T
.
50pF
RT
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
500W
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
CL
Octal Link
Test Circuits for All Outputs
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
Pulse Width
Octal Link
Octal Link
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
3.5V
0.3V
VOL
tPHZ
0.3V
VOH
1.5V
0V
Octal Link
0V
Octal Link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXX
IDT
XX
FCT
Device Type
Temp. Range
XX
Package
X
Process
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
Blank
Industrial
SO
SOG
Q
QG
Small Outline IC
SOIC - Green
Quarter-size Small Outline Package
QSOP - Green
543AT
543CT
543DT
Fast CMOS Octal Latched Transceiver
74
– 40°C to +85°C
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
7
for Tech Support:
[email protected]
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