IDT IDT74FCT823CTQ High-performance cmos bus interface register Datasheet

IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTER
DESCRIPTION:
FEATURES:
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•
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IDT74FCT823AT/CT
A and C grades
Low input and output leakage ≤1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
High Drive outputs (-15mA IOH, 48mA IOL)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in the SOIC and QSOP packages
The FCT823T series is built using an advanced dual metal CMOS
technology. The FCT823T series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying
parity. The FCT823T is a 9-bit wide buffered register with Clock Enable
(EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance
microprogrammed systems.
The FCT823T high-performance interface family can drive large capacitive
loads, while providing low-capacitance bus loading at both inputs and
outputs. All inputs have clamp diodes and all outputs are designed for lowcapacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0
DN
EN
CLR
D
CL
Q
D
CP Q
CL
Q
CP Q
CP
OE
Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
YN
JUNE 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-5487/4
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
OE
1
24
VCC
D0
2
23
Y0
D1
3
22
Y1
D2
4
21
Y2
D3
5
20
Y3
D4
6
19
Y4
D5
7
18
Y5
D6
8
17
Y6
D7
9
16
Y7
D8
10
15
Y8
CLR
11
14
EN
GND
12
13
CP
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
CIN
Input Capacitance
VIN = 0V
6
10
Unit
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
I/O
FUNCTION TABLE(1)
Description
Dx
I
D Flip-Flop Data Inputs
CLR
I
When the clear input is LOW and OE is LOW, the
Qx outputs are LOW. When the clear input is HIGH,
data can be entered into the register.
CP
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Yx
O
Register 3-State Outputs
EN
I
Clock Enable. When the clock enable is LOW, data
on the Dx output is transferred to the Qx output on the
LOW-to-HIGH transition. When the clock enable is
HIGH, the Qx outputs do not change state, regardless
of the data or clock input transitions.
OE
I
OE
H
H
H
L
H
L
H
H
L
L
Output Control. When the OE is HIGH, the Yx
outputs are in the high-impedance state. When the
OE is LOW, the TRUE register data is present at the
Yx outputs.
CLR
H
H
L
L
H
H
H
H
H
H
Inputs
EN
L
L
X
X
H
H
L
L
L
L
Dx
L
H
X
X
X
X
L
H
L
H
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
NC = No Change
↑ = LOW-to-HIGH Transition
Z = High Impedance
2
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Internal/
Outputs
Qx
Yx
L
Z
H
Z
L
Z
L
L
NC
Z
NC
NC
L
Z
H
Z
L
L
H
H
Function
High Z
Clear
Hold
Load
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
—
—
±1
µA
IIL
Input LOW Current(4)
VCC = Max.
VI = 0.5V
—
—
±1
µA
High Impedance Output Current(4)
VCC = Max., VI = VCC (Max.)
VI = 2.7V
—
—
±1
µA
II
Input HIGH Current(4)
VCC = Max., VI = VCC (Max.)
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
VH
Input Hysteresis
ICC
Quiescent Power Supply Current
IOZH
IOZL
VI = 0.5V
—
VCC = Max.
VIN = GND or VCC
—
—
±1
—
—
±1
—
–0.7
–1.2
V
—
200
—
mV
—
0.01
1
mA
Min.
2.4
2
—
Typ.(2)
3.3
3
0.3
Max.
—
—
0.5
Unit
V
–60
–120
–225
mA
—
—
±1
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Parameter
Output HIGH Voltage
Test Conditions(1)
IOH = –8mA
IOH = –15mA
IOL = 48mA
VOL
Output LOW Voltage
IOS
Short Circuit Current
VCC = Min
VIN = VIH or VIL
VCC = Min
VIN = VIH or VIL
VCC = Max., VO = GND(3)
IOFF
Input/Output Power Off Leakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
3
V
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
—
0.5
2
mA
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
VIN = VCC
VIN = GND
—
1.5
3.5
mA
OE = EN = GND
One Bit Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
—
2
5.5
VCC = Max.
Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
—
3.8
7.3(5)
VIN = 3.4V
VIN = GND
—
6
16.3(5)
Symbol
Parameter
ΔICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OE = EN = GND
One Input Toggling
50% Duty Cycle
Total Power Supply Current(6)
IC
50% Duty Cycle
OE = EN = GND
Eight Bits Toggling
at fi = 2.5MHz
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT823AT
Symbol
Parameter
FCT823CT
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
10
1.5
6
ns
1.5
20
1.5
12.5
ns
tPLH
Propagation Delay
CL = 50pF
tPHL
CP to Yx (OE = LOW)
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
tSU
Set-up Time HIGH or LOW Dx to CP
CL = 50pF
4
—
3
—
ns
tH
Hold Time HIGH or LOW Dx to CP
RL = 500Ω
2
—
1.5
—
ns
tSU
Set-up Time HIGH or LOW EN to CP
4
—
3
—
ns
tH
Hold Time HIGH or LOW EN to CP
2
—
0
—
ns
1.5
14
1.5
8
ns
tPHL
Propagation Delay, CLR to Yx
tREM
Recovery Time CLR to CP
6
—
6
—
ns
tW
Clock Pulse Width HIGH or LOW
7
—
6
—
ns
tW
CLR Pulse Width LOW
6
—
6
—
ns
1.5
12
1.5
7
ns
1.5
23
1.5
12.5
ns
1.5
7
1.5
6
ns
1.5
8
1.5
6.5
ns
tPZH
Output Enable Time OE to Yx
tPZL
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
tPHZ
tPLZ
Output Disable Time OE to Yx
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
5
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
SWITCH POSITION
7.0V
500W
V OUT
VIN
Pulse
Generator
D.U.T
.
50pF
RT
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
500W
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
CL
Octal Link
Test Circuits for All Outputs
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
Pulse Width
Octal Link
Octal Link
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
3.5V
0.3V
VOL
tPHZ
0.3V
VOH
1.5V
0V
Octal Link
0V
Octal Link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXX
XX
FCT
Temp. Range
Device Type
X
Package
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SO
SOG
Q
QG
Small Outline IC
SOIC - Green
Quarter-size Small Outline Package
QSOP - Green
823AT
823CT
Bus Interface Register
74
- 40°C to +85°C
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