IDT IDT74LVCH16245APV 3.3v cmos 16-bit bus transceiver with 3-state outputs, 5 volt tolerant i/o and bus-hold Datasheet

IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH16245A
3.3V CMOS 16-BIT
BUS TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
μ W typ. static)
• CMOS power levels (0.4μ
• All inputs, outputs, and I/O are 5V tolerant
• Available in SSSOP and TSSOP packages
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and
Output Enable controls are designed to operate this device as either two
independent 8-bit transceivers or one 16-bit transceiver. The direction
control pin (DIR) controls the direction of data flow. The output enable pin
(OE) overrides the direction control and disables both ports. All inputs are
designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16245A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16245A has “bus-hold” which retains the inputs' last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1DIR
24
1
2DIR
25
48
1OE
1A1
2OE
47
2A1
2
36
13
1B1
1A2
2A2
3
14
1B2
1A3
2A3
16
1B3
2B3
32
43
2A4
6
17
1B4
1A5
2B4
41
2A5
30
8
19
1B5
1A6
40
2A6
20
1B6
38
2A7
22
1B7
2B7
37
2A8
12
2B6
27
11
1A8
2B5
29
9
1A7
2B2
33
44
5
1A4
2B1
35
46
26
23
1B8
2B8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 2008
1
© 2006 Integrated Device Technology, Inc.
DSC-4596/4
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
1DIR
1
48
1OE
1B1
2
47
1A1
1B2
3
46
1A2
GND
4
45
GND
1B3
5
44
1A3
43
1A4
1B4
6
VCC
7
42
VCC
1B5
8
41
1A5
1B6
9
40
1A6
GND
10
39
GND
1B7
11
38
1A7
1B8
12
37
1A8
2B1
13
36
2A1
Description
Max
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
–50
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
14
35
2A2
GND
15
34
GND
2B3
16
33
2A3
2B4
17
32
2A4
VCC
18
31
VCC
xOE
2B5
19
30
2A5
xDIR
Direction Control Input
xAx
Side A Inputs or 3-State Outputs(1)
xBx
Side B Inputs or 3-State Outputs(1)
PIN DESCRIPTION
Pin Names
20
29
2A6
GND
21
28
GND
2B7
22
27
2A7
2B8
23
26
2A8
2DIR
24
25
2OE
Unit
NOTE:
1. As applicable to the device type.
2B2
2B6
Unit
Description
Output Enable Inputs (Active LOW)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH 8-BIT SECTION)(1)
Inputs
SSOP/ TSSOP
TOP VIEW
xOE
xDIR
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
Isolation
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
2
Outputs
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
µA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
ΔICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
—
—
10
mV
µA
3.6 ≤ VIN ≤ 5.5V(2)
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
—
—
10
500
µA
Min.
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
—
—
—
IIH
IIL
Quiescent Power Supply Current
Variation
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
Bus-Hold Input Sustain Current
VCC = 3V
Bus-Hold Input Sustain Current
VCC = 2.3V
Bus-Hold Input Overdrive Current
VCC = 3.6V
VI = 2V
IBHL
IBHH
IBHL
IBHHO
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
VI = 0.7V
—
—
—
VI = 0 to 3.6V
—
—
±500
µA
µA
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
VOL
Test Conditions(1)
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
V
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC – 0.2
—
VCC = 2.3V
IOH = – 6mA
2
—
VCC = 2.3V
IOH = – 12mA
1.7
—
VCC = 2.7V
2.2
—
VCC = 3V
2.4
—
VCC = 3V
IOH = – 24mA
2.2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3V
IOL = 24mA
—
0.55
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance per Transceiver Outputs enabled
CPD
Power Dissipation Capacitance per Transceiver Outputs disabled
Test Conditions
Typical
Unit
CL = 0pF, f = 10Mhz
40
pF
4
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V
Symbol
VCC = 3.3V ± 0.3V
Parameter
Min.
Max.
Min.
Max.
Unit
tPLH
Propagation Delay
—
4.7
1
4
ns
tPHL
xAx to xBx, xBx to xAx
tPZH
Output Enable Time
—
6.7
1.5
5.5
ns
tPZL
xOE to xAx or xBx
tPHZ
Output Disable Time
—
7.1
1.5
6.6
ns
tPLZ
xOE to xAx or xBx
—
—
—
1
ns
tSK(o)
Output Skew(2)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
VCC(2)= 2.5V±0.2V
Unit
2 x Vcc
V
6
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
tPLH
tPHL
OUTPUT
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
LVC Link
Propagation Delay
Pulse (1, 2)
Generator
tPZL
GND
500Ω
VOUT
OUTPUT
SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY
OPEN
HIGH
D.U.T.
500Ω
RT
CL
Test Circuit for All Outputs
VIH
VT
0V
CONTROL
INPUT
Open
VIN
DISABLE
ENABLE
VLOAD
VCC
tPLZ
VLOAD/2
VT
VLOAD/2
VLZ
VOL
tPHZ
VOH
VHZ
0V
VT
0V
LVC Link
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
SWITCH POSITION
Switch
Open Drain
Disable Low
Enable Low
VLOAD
ASYNCHRONOUS
CONTROL
Disable High
Enable High
GND
SYNCHRONOUS
CONTROL
All Other Tests
Open
OUTPUT 1
tPLH1
tSK (x)
tSK (x)
tPLH2
tH
Set-up, Hold, and Release Times
VOH
VT
VOL
VT
tW
HIGH-LOW-HIGH
PULSE
VT
LVC Link
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tSU
LOW-HIGH-LOW
PULSE
VOH
VT
VOL
OUTPUT 2
tREM
LVC Link
VIH
VT
0V
tPHL1
tH
TIMING
INPUT
Test
INPUT
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
LVC X
XX
Bus-Hold
Temp. Range
XX
Family
XX
XXXX
Device Type Package
PV
PVG
PA
PAG
Shrink Small Outline Package
SSOP - Green
Thin Shrink Small Outline Package
TSSOP - Green
245A 16-Bit Bus Transceiver with 3-State Outputs
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16
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H
Bus-hold
74
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6
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