ETC1 IMIC9716J 100 mhz clock generator with sscg and power management for mobile application Datasheet

C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Product Features
Frequency Table
SEL 100/66#
0
1
•
Supplies:
•
2 Ref clocks
2 Host (CPU) clocks
•
1 free running and 5 PCI Clocks
•
1 48MHz fixed clock
•
1 48 or 24 MHz fixed clock
•
Separate supply pins for mixed (3.3/2.5V) voltage
application.
•
100 or 66 MHz CPU clock operation
•
-1.5% Spread Spectrum modulation for reducing
EMI
•
Rich Power Management Functions.
•
28-pin SSOP & TSSOP packages for minimum
board space.
Block Diagram
CPU Clock
66.66 MHz
100.00 MHz
PCI Clock
33.33 MHz
33.33 MHz
Pin Configuration
SEL48#
REF2
VDDR
XIN
XOUT
REF1
OSC
SS#
48-24M
SEL48#
PLL
48-24M/TS#
VDDC
CPU (1,2)
SEL100/66#
CS#
PD#
PS#
SS#
PLL
PCI_F
VSS
XIN
XOUT
PCI_F
PCI1
PCI2
VSS
VDDP
PCI3
PCI4
PCI5
VDDF
48M
48-24/TS#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDR
REF/SEL48#
REF1/SS#
VDDC
CPU1
CPU2
VSS
VSS
PS#
VDD
CS#
PD#
SEL100/66#
VSS
VDDP
PCI (1:3)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 1 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Pin Description
PIN No.
2
Pin Name
XIN
PWR
VDD
I/O
I
TYPE
XTAL4
Description
On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
O-chip reference oscillator output pin. Drives an external
parallel resonant crystal (14.318 MHz) when an externally
generated reference signal is used.
3.3 volt power supply for core logic.
Clock outputs. CPU frequency table specified on page 1.
Powers down device when LOW
When signal is LOW, stops CPU clocks in low state.
Frequency select input pins. See frequency select table on
page 1. NO INTERNAL PULLUP RESISTOR IS PROVIDED
BY DEVICE
2.5V power for CPU and Host clock outputs.
Free running PCI clock 3.3V. Does not stop when PS# is at a
logic LOW level
PCI output clocks. See frequency table of page 1.
3
XOUT
VDD
O
XTAL4
19
23, 24
17
18
16
VDD
CPU (1,2)
PD#
CS#
SEL100/66#
VDDC
-
P
O
I
I
I
PWR
C100S
INP3U
INP3U
INP3
25
4
VDDC
PCI_F
VDDP
P
O
PWR
P100S
5,6,9,
10,11
20
8
PCI(1:5)
VDDP
O
P100S
PS#
VDDP
-
I
P
INP3U
PWR
13
14
48M
48-24M/TS#
VDDF
VDDF
O
I/O
U48
U48BU
26
REF1/SS#
VDDR
I/O
U48BU
27
REF2/SEL48
#
VDDR
I/O
U48BU
12
1, 7, 15,
21, 22
28
VDDF
VSS
-
P
P
PWR
PWR
When signal is LOW, stops all PCI clocks in low state.
3.3 Volt power supply pins for free running PCI clock output
buffer.
Fixed 48 MHz clock.
Power up selectable 48 or 24 MHz clock. If strapped LOW at
powerup causes the devices outputs to be tri-stated until the
next power up sequence occurs.
At power up this pin determines if the device’s spread
spectrum modulation feature is enabled or disabled. After
power up this pin becomes a reference clock output. A 0 (logic
low) enables SSCG and a 1 (logic high) disables SSCG.
At power up this pin determine the frequency of the clock at pin
14. If it is LOW, the clock will be 48 MHz, if HIGH the clock will
be 24 MHz. After power up this pin will become a reference
clock output.
Power for fixed clock output buffer.
Ground pins for device.
VDDR
-
P
PWR
Power for Reference Oscillator output buffer.
Notes
1. INP3U pins have internal pullup resistors that will guarantee to a logic1 (high) level if no connection is made to the
device’s pin. INP3 pins do not contain this function and must be electrically connected to VDD or VSS by external
circuitry to ensure a valid logic 1 or 0 is sensed.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 2 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Frequency Selection Table
Outputs
CPU
PCI
Descriptions
48-24M/TS#
at Power UP
SEL
66/100
48M
48/24M
All Outputs Tri-State
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
66 MHz
1
0
66.66 MHz
33.33 MHz
48 MHz
24/48 MHz
100 MHz
1
Test Mode
0
1
100.00 MHz
33.33 MHz
48 MHz
24/48 MHz
1
7.16 MHz
2.38 MHz
7.16 MHz
7.16/3.58 MHz
Power Management Functions
PS#
CS#
PD#
CPU
48M
PCI
PCI_F
VCOs
X
X
0
LOW
LOW
LOW
LOW
OFF
1
0
1
LOW
ON
ON
ON
ON
0
1
X
ON
ON
LOW
ON
ON
CS# is an input clock synthesizer. It is used to turn off the CPU clocks for low power operation. CS# is asserted
asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU Clock)
and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU
clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse. CPU clock on latency need to be 2 or 3 CPU clocks periods in time
and CPU clock off latency needs to be 2 or 3 CPU clocks periods in time.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 3 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Power Management Timing
CPU
CS#
CPU STOP TIMING
CPU
PCI
REF
48M
PD#
POWER DOWN TIMING
PCI
PS#
PCI STOP TIMING
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal clocks are not running
after the device is put in power down. When PD# is active low, all clocks need to be driven to a low value and held prior
to turning off the VCO’s and the Crystal. The power-up latency needs to be less than 3 mS. The power down latency
should be as short as possible but conforming to the sequence requirements shown below. AS# and CS# are
considered to be don’t cares during the power down operations.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 4 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Power Management Timing
Signal
CS#
PD#
Signal State
Latency
No. of rising edges of free
running PCI CLOCK (PCIF)
0 (disabled)
1
1 (enabled)
1
1 (cold start/normal operation)
3 mS
0 (power down)
1
NOTES:
1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable
goes low/high to the first valid clock comes out of the device.
Spectrum Spread Clocking
Non -Spread
Reduction
Spread
Spectrum Analysis
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 5 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Spectrum Spreading Selection Table
Min
(MHz)
Center
(MHz)
Max
(MHz)
CPU
Frequency
% OF FREQUENCY
SPREADING
MODE
98.51285
99.2634
100.01397
100.00
1.5% (-1.5% + 0%)
Down Spread
65.6649
66.166
66.667
66.66
1.5% (1.5% + 0%)
Down Spread
Test and Measurement Condition
Out Put
Buffer
Test Point
Specified Test Load Condition
CL
Clock Output Wave form
3.3 V Clocking Interface
PCI ( 1:5) , 48-24M, REF(1,2)
tHKP
Duty Cycle
3.3 V
2.4 V
1.5 V
0.4 V
0.0 V
2.5 V Clocking Interface
CPU (1,2)
tHKP
Duty Cycle
2.5 V
2.0 V
1.25 V
0.4 V
0.0 V
tprise
tpfall
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
tprise
tpfall
Rev. 1.0
4/28/2000
Page 6 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Absolute Maximum Ratings
Voltage Relative to VSS:
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
should be constrained to the range:
VSS<(Vin)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
-0.3V
Voltage Relative to VDD:
0.3V
Storage Temperature:
0ºC to + 125ºC
Operating Temperature:
0ºC to +70ºC
Maximum Power Supply:
7V
DC Parameters
Characteristic
Symbol
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
IOL = 4mA
Output High Voltage
IOH = 4mA
Tri-State leakage Current
Dynamic Supply Current
(2.5 Volt Supply)
Dynamic Supply Current
(3.3 Volt Supply)
Power Down Mode
Power Down Mode
Min
Typ
VIL
VIH
IIL
IIH
VOL
2.0
-
-
VOH
Ioz
Idd266
Idd2100
Idd366
Idd3100
I2.5PD
I3.3PD
Max
Units
-
0.8
-66
5
0.4
Vdc
Vdc
µA
µA
Vdc
2.4
-
-
Vdc
-
-
10
35
45
100
120
200 uA
100 uA
µA
mA
mA
mA
mA
mA
mA
Conditions
All Outputs (see buffer spec)
All Outputs Using 3.3V Power
(see buffer spec)
TS# = 1, 100/66 = 0, CS# = 1
TS# = 1, 100/66 = 0, CS# = 1
TS# = 1, 100/66 = 1, CS# = 1
TS# = 1, 100/66 = 1, CS# = 1
PD# at logic low level
PD# at logic low level
VDD = VDDF = VDDP=VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 7 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
AC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Output Duty Cycle
-
45
50
55
%
CPU and CPU/2 = Measured at 1.25V
all others measured at 1.50V
CPU to PCI Offset
tOFF
1
-
4
ns
CPU = 20 pF load Measured at 1.25V
PCI = 30 pF load Measure at 1.50V
tSKEW
-
-
250
ps
CPU = 20 pF load Measured at 1.25V
PCI = 30 pF Load Measured at 1.5V
∆P
-
-
+250
ps
CPU
∆P
-
-
+ 500
pS
PCI Only
Buffer out Skew All CPU
and PCI Buffer Outputs
∆Period Adjacent Cycles
∆Period Adjacent Cycles
VDD = VDDF = VDDP =VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = 0ºC to +70ºC
AC Skew Requirements
Characteristic
Bank Skew
CPU
Cycle to Cycle Jitters
175pS
48 MHz
PCI, PCI_F
Ref
VDD
+/- 250pS
Skew, Jitters Measure Point
2.5V
1.25V
n/a
+/- 500pS
3.3V
1.5V
500pS
+/- 500pS
3.3V
1.5V
n/a
+/- 500pS
3.3V
1.5V
Offset Requirements
Characteristic
Bank Offset
Measurement Loads (lumped)
Measure Points
CPU to PCI, PCI-5
1.5-4.0nS CPU leads
CPU @ 20pF, PCI @ 30 pF
CPU @ 1.25V, PCI @ 1.5V
DC Buffer Characteristics for CPU Outputs
Characteristic
Symbol
Pull-Up Current Min
IOHmin
Pull-Up Current Max
IOHmax
Pull-Down Current Min
IOLmin
Pull-Down Current Max
Min
-82
81
Typ
Max
-
Units
Conditions
mA
Vout = 1.0 V
-67
mA
Vout = 2.375 V
-
mA
Vout = 1.2 V
IOLmax
-
-
60
mA
Vout = 0.3 V
Rise Time Between 0.4 V and 2.4 V
TR
0.4
-
1.6
nS
20 pF Load
Fall Time Between 0.4 V and 2.4 V
TF
0.5
-
1.6
nS
20 pF Load
VDD = VDDF = VDDP = VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 8 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
DC Buffer Characteristics for 48M, 48-24M and REF Outputs
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
IOHmin
-29
-
-
mA
Vout = 1.0 V
Pull-Up Current Max
IOHmax
-
-
-23
mA
Vout = 3.135 V
Pull-Down Current Min
IOLmin
29
-
-
mA
Vout = 1.95 V
Pull-Down Current Max
IOLmax
-
-
27
mA
Vout = 0.4 V
Rise Time Between 0.4 V and 2.4 V
TR
0.5
-
2.0
nS
20 pF Load
Fall Time Between 0.4 V and 2.4 V
TF
0.5
-
2.0
nS
20 pF Load
VDD = VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = 0ºC to +70ºC
DC Buffer Characteristics for PCI_F, PCI (1:5)
Characteristic
Symbol
Pull-Up Current Min
IOHmin
Pull-Up Current Max
IOHmax
Pull-Down Current Min
IOLmin
Pull-Down Current Max
IOLmax
Rise Time Between 0.4 V and 2.4 V
Fall Time Between 0.4 V and 2.4 V
Min
-33
Typ
Max
Units
Conditions
-
-
mA
Vout = 1.0 V
-
-
-33
mA
Vout = 3.135 V
30
-
-
mA
Vout = 1.95 V
-
-
38
mA
Vout = 0.4 V
TR
0.5
-
2.0
nS
30 pF Load
TF
0.5
-
2.0
nS
30 pF Load
VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 9 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Crystal and Reference Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Frequency
Fo
12.00
14.31818
16.00
MHz
Tolerance
TC
-
-
+/-100
PPM
TS
-
-
+/- 100
PPM
Mode
OM
-
-
-
Pin Capacitance
CP
DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Startup time
Ts
-
-
30
µS
Load Capacitance
CL
-
20
-
pF
Effective Series
resistance
R1
-
-
40
Ohms
Power Dissipation
DL
-
-
0.10
mW
Shunt Capacitance
CO
-
--
7
pF
X1 and X2 Load
CL
5
Calibration note 1
Stability (Ta -10 to +60C) note 1
Parallel Resonant
pF
32
Conditions
pF
Capacitance of XIN and Xout pins
Note 1
Note 1
Internal crystal loading capacitors on
each pin (to ground)
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore
2.0 pF
Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore
18.0 pF
the total parasitic capacitance would therefore be
= 20.0 pF(matching CL)
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 10 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Package Drawing and Dimensions
28 Pin SSOP Outline Dimensions
INCHES
SYMBOL
C
L
H
E
a
D
A2
A1
B
e
A
MILLIMETERS
MIN
NOM
MAX
MIN
NOM
MAX
A
0.068
0.073
0.078
1.73
1.86
1.99
A1
0.002
0.005
0.008
0.05
0.13
0.21
A2
0.066
0.068
0.070
1.68
1.73
1.78
B
0.010
0.012
0.015
0.25
0.30
0.38
C
0.005
0.006
0.009
0.13
0.15
0.22
D
0.397
0.402
0.407
10.07
10.20
10.33
E
0.205
0.209
0.212
5.20
5.30
5.38
e
0.0256 BSC
0.65 BSC
H
0.301`
0.307
0.311
7.65
7.80
7.90
a
0°
4°
8°
0°
4°
8°
L
0.022
0.030
0.037
0.55
0.75
0.95
28 Pin TSSOP Outline Dimensions
INCHES
SYMBOL
MIN
A
-
NOM
MILLIMETERS
MAX
MIN
-
0.047
-
NOM
MAX
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.031
0.039
0.041
0.80
1.00
1.05
B
0.007
-
0.012
0.19
-
0.30
C
0.004
-
0.008
0.09
-
0.20
D
0.378
0.382
0.386
9.60
9.70
9.80
E
0.169
0.173
0.177
4.30
4.40
4.50
e
0.026 BSC
0.65 BSC
H
0.244
0.252
0.260
6.20
6.40
6.60
L
0.018
0.024
0.030
0.45
0.60
0.75
a
0º
-
0º
-
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
8º
Rev. 1.0
8º
4/28/2000
Page 11 of 12
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
Ordering Information
Part Number
Package Type
IMIC9716JY
28 PIN SSOP
Commercial, 0ºC to +70ºC
IMIC9716JT
28 PIN TSSOP
Commercial, 0ºC to +70ºC
Note:
Production Flow
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example:
IMI
C9716J
Date Code, Lot #
IMIC9716JY
Package
Y = SSOP
T = TSSOP
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/28/2000
Page 12 of 12
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