IMP IMP705C/D Low-power î¼p supervisor circuit Datasheet

IMP705/6/7/8, 8 13L
POWER MANAGEMENT
Low-Power µP Supervisor Circuits
– Watc hdog timer
– Br o wnout det ection
– Po w er suppl y monit or
The IMP705/706/707/708 and IMP813L CMOS supervisor circuits
monitor power-supply and battery voltage level, and µP/µC operation.
Compared to pin-compatible devices offered by Maxim Integrated
Products, IMP devices feature 60 percent lower maximum supply current.
The family offers several functional options. Each device generates a
reset signal during power-up, power-down and during brownout
conditions. A reset is generated when the supply drops below
4.65V (IMP705/707/813L) or 4.40V (IMP706/708). For 3V power supply
applications, refer to the IMP705P/R/S/T data sheet. In addition, the
IMP705/706/813L feature a 1.6 second watchdog timer. The IMP707/708
have both active-HIGH and active-LOW reset outputs but no watchdog
function. The IMP813L has the same pin-out and functions as the IMP705
but has an active-HIGH reset output. A versatile power-fail circuit has a
1.25V threshold, useful in checking battery levels and non-5V supplies. All
devices have a manual reset (MR) input. The watchdog timer output will
trigger a reset if connected to MR.
Block Diagrams
Transition
Detector
Watchdog
Timer
Computers and embedded controllers
Battery-operated systems
Intelligent instruments
Wireless communication systems
PDAs and handheld equipment
RESET
VCC
0.25mA
Timebase
0.25mA
RESET
Generator
MR
RESET
(RESET)
(IMP813L)
+
+
Applications
WDO
VCC
VCC
◆ Improved replacements for the Maxim
MAX705/6/7/8, MAX813L
– 140µA maximum supply current
– 60% improvement
◆ Precision power supply monitor
– 4.65V threshold (IMP705/707/813L)
– 4.40V threshold (IMP706/8)
◆ Debounced manual reset input
◆ Voltage monitor
– 1.25V threshold
– Battery monitor/Auxiliary supply monitor
◆ Watchdog timer (IMP705/706/813L)
◆ 200ms reset pulse width
◆ Active HIGH reset output (IMP707/708/813L)
◆ MicroSO package
◆
◆
◆
◆
◆
All devices are available in 8-pin DIP, SO and MicroSO packages.
WDI
Key Features
MR
RESET
Generator
–
+
4.65V (IMP705/813L)
4.40V (IMP706)
IMP705
IMP706
IMP813L
1.25V
PFO
–
+
PFI
PFO
1.25V
–
IMP707
IMP708
GND
© 1999 IMP, Inc.
–
4.65V (IMP707)
4.40V (IMP708)
+
PFI
RESET
+
VCC
705_01.eps
408-432-9100/www.impweb.com
705_02.eps
GND
1
IMP705/6/7/8, 8 13L
Pin Configuration
MicroSO
DIP/SO
MR
1
VCC
2
GND
3
PFI
4
IMP707
IMP708
8
RESET
MR
1
7
RESET
VCC
2
6
NC
GND
3
5
PFO
PFI
4
IMP705
IMP706
(IMP813L)
8
WDO
RESET
1
7
RESET (RESET)
RESET
2
6
WDI
MR
3
5
PFO
VCC
4
IMP707
IMP708
8
NC
7
PFO
6
PFI
5
GND
RESET (RESET)
1
WDO
2
MR
3
VCC
4
IMP705
IMP706
(IMP813L)
8
WDI
7
PFO
6
PFI
5
GND
705_03.eps
Ordering Information
Part Number
Reset Threshold (V)
Temperature Range
IMP705 Active LOW Reset, Watchdog Output and Manual RESET
IMP705CPA
IMP705CSA
IMP705CUA
IMP705C/D
IMP705EPA
IMP705ESA
IMP706ESA
4.65
4.65
4.65
4.65
4.65
4.65
4.40
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Pins-Package
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
8-SO
IMP706 Active LOW Reset, Watchdog Output and Manual RESET
IMP706CPA
IMP706CSA
IMP706CUA
IMP706C/D
IMP706EPA
IMP706ESA
4.40
4.40
4.40
4.40
4.40
4.40
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
IMP707 Active LOW & HIGH Reset with Manual RESET
IMP707CPA
IMP707CSA
IMP707CUA
IMP707C/D
IMP707EPA
IMP707ESA
4.65
4.65
4.65
4.65
4.65
4.65
IMP708 Active LOW & HIGH Reset with Manual RESET
IMP708CPA
IMP708CSA
IMP708CUA
IMP708C/D
IMP708EPA
IMP708ESA
4.40
4.40
4.40
4.40
4.40
4.40
IMP813L Active HIGH Reset, Watchdog Output and Manual RESET
IMP813LCPA
IMP813LCSA
IMP813LCUA
IMP813LC/D
IMP813LEPA
IMP813LESA
2
4.65
4.65
4.65
4.65
4.65
4.65
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
408-432-9100/www.impweb.com
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
© 1999 IMP, Inc.
IMP705/6/7/8, 8 13L
Absolute Maximum Ratings
Pin Terminal Voltage with Respect to Ground
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6.0V
All other inputs1 . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to (VCC + 0.3V)
Input Current at VCC and GND . . . . . . . . . . 20mA
Output Current: All outputs . . . . . . . . . . . . . 20mA
Rate of Rise at VCC . . . . . . . . . . . . . . . . . . . . . 100V/µs
Plastic DIP Power Dissipation . . . . . . . . . . . 700 mW
(Derate 9 mW/°C above 70°C)
SO Power Dissipation . . . . . . . . . . . . . . . . . 470 mW
(Derate 5.9 mW/°C above 70°C)
MicroSO Power Dissipation . . . . . . . . . . . . . 330mW
(Derate 4.1 mW/°C above 70°C)
Operating Temperature Range
IMP705E/706E/707E/708E/813LE . . . . . . . –40°C to 85°C
IMP706C/707C/708C/813LC . . . . . . . . . . . 0°C to 70°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 160°C
Lead Temperature Soldering(10 sec) . . . . . . 300°C
Note: 1. The input voltage limits on PFI and MR can be exceeded if
the input current is less than 10mA.
These are stress ratings only and functional operation is not implied.
Electrical Characteristics
Unless otherwise noted, VCC = 4.75V to 5.5V for the IMP705/707/813L. VCC = 4.5V to 5.5V for the IMP706/708 and over the
operating temperature range.
Parameter
Operating Voltage Range
Symbol
Conditions
Min
VCC
IMP705/6/7/8C
1.2
Supply Current
ICC
RESET Threshold
VRT
RESET Threshold Hysteresis
RESET Pulse Width
MR Pulse Width
MR to RESET Out Delay
MR Input Threshold
tRS
tMR
tMD
VIH
VIL
MR Pull-up Current
RESET Output Voltage
RESET Output Voltage
Watchdog Timeout Period
WDI Pulse Width
WDI Input Threshold
WDI Input Current
WDO Output Voltage
PFI Input Threshold
PFI Input Current
PFO Output Voltage
tWD
tWP
VIH
VIL
Typ
Max
Units
5.5
V
IMP813L
1.1
5.5
IMP705/6/7/8E, IMP813lE
IMP705C/706C/813LC
IMP705E, IMP706E, IMP813LE
IMP707C, IMP708C
IMP707E, IMP708E
IMP705, IMP707, IMP813L, Note 2
IMP706, IMP708, Note 2
Note 2
Note 2
1.2
5.5
140
140
140
140
4.75
4.50
4.50
4.25
140
0.15
75
75
50
50
4.65
4.40
40
200
Note 2
280
0.25
2.0
MR = 0V
ISOURCE = 800µA
ISINK = 3.2mA
IMP705/6/7/8, VCC = 1.2V, ISINK = 100µA
IMP707/708/813L, ISOURCE = 800µA
IMP707/708, ISINK = 1.2mA
IMP813L, ISINK = 3.2mA
IMP813L, VCC =1.2V, ISOURCE = 4µA
IMP705/706/813L
VIL = 0.4V, VIH = 0.8VCC
IMP705/706/813L, VCC = 5V
IMP705/706/813L, WDI = VCC
IMP705/706/813L, WDI = 0V
IMP705/706/813L, ISOURCE = 800µA
IMP705/706/813L, ISINK = 1.2mA
VCC = 5V
ISOURCE = 800µA
ISINK = 3.2mA
100
VCC - 1.5V
250
0.8
600
µA
V
mV
ms
µs
µs
V
µA
V
0.4
0.3
VCC - 1.5V
V
0.4
0.4
0.9
1.00
50
3.5
–150
VCC - 1.5V
1.2
– 25
VCC - 1.5V
1.60
50
– 50
2.25
0.8
150
s
ns
V
µA
V
1.25
0.01
0.4
1.3
25
V
nA
V
0.4
Notes: 2. RESET (IMP705/6/7/8), RESET (IMP707/8, IMP813L)
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP705/6/7/8, 8 13L
Pin Descriptions
Pin Number
IMP705/706
IMP707/708
IMP813L
DIP/SO MicroSO DIP/SO MicroSO DIP/SO MicroSO Name
1
3
1
3
1
3
MR
2
3
4
5
2
3
4
5
2
3
4
5
VCC
GND
4
6
4
6
4
6
PFI
5
7
5
7
5
7
PFO
6
8
—
—
6
8
WDI
—
—
6
—
—
—
NC
7
1
7
1
—
—
RESET
8
2
—
—
8
2
WDO
—
—
8
2
7
1
RESET
Function
Manual RESET input. The active LOW input triggers a reset
pulse. A 250µA pull-up current allows the pin to be driven
by TTL / CMOS logic or shorted to ground with a switch.
+5V power supply input.
Ground reference for all signals.
Power-fail voltage monitor input. With PFI less than
1.25V, PFO goes low. Connect PFI to ground or VCC
when not used.
Power-fail output. The output is active LOW and sinks
current when PFI is less than 1.25V.
Watchdog input. WDI controls the internal watchdog
timer. A HIGH or LOW signal for 1.6sec at WDI
allows the internal timer to run-out, setting WDO LOW.
The watchdog function is disabled by floating WDI or
by connecting WDI to a high-impedance three-state
buffer. The internal watchdog timer clears when:
RESET is asserted; WDI is three-stated; or WDI sees
a rising or falling edge.
Not connected.
Active-LOW reset output. Pulses LOW for 200ms
when triggered, and stays low whenever VCC is below
the reset threshold (IMP705: 4.65V, IMP705J: 4.00V,
IMP706: 4.40V). RESET remains LOW for 200ms
after VCC rises above the RESET threshold or MR
goes from LOW to HIGH. A watchdog timeout will not
trigger RESET unless WDO is connected to MR.
Watchdog output. WDO pulls LOW when the 1.6 sec
internal watchdog timer times-out and does not go
HIGH until the watchdog is cleared. In addition, when
VCC is below the reset threshold, WDO remains low.
Unlike RESET, WDO does not have a minimum pulse
width and as soon as VCC exceeds the reset
threshold, WDO goes HIGH with no delay.
Active-HIGH reset output. RESET is the inverse of
RESET. The IMP813L has only a RESET output.
Feature Summary
Power-fail detector
Brownout detection
Manual RESET input
Power-up/down RESET
Watchdog timer
Active-HIGH RESET output
Active-LOW RESET output
RESET threshold
4
IMP705
IMP706
IMP707
IMP708
IMP813L
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
4.65V/4.00V
■
4.40V
■
■
4.65V
■
■
4.40V
■
■
■
■
■
■
408-432-9100/www.impweb.com
4.65V
© 1999 IMP, Inc.
IMP705/6/7/8, 8 13L
Detail Descriptions
RESET/RESET Operation
Manual Reset (MR)
The RESET/RESET signals are designed to start a µP/µC in a
known state or return the system to a known state.
The active-LOW manual reset input is pulled high by a 250µA
pull-up current and can be driven low by CMOS/TTL logic or a
mechanical switch to ground. An external debounce circuit is
unnecessary since the 140ms minimum reset time will debounce
mechanical pushbutton switches.
The IMP707/708 have two RESET outputs, one active-HIGH
RESET and one active-LOW RESET output. The IMP813L has
only an active-HIGH output. RESET is simply the complement
of RESET.
RESET is guaranteed to be LOW with VCC above 1.2V. During a
power-up sequence, RESET remains low until the supply rises
above the threshold level, either 4.65V, 4.40V or 4.00V.. RESET goes
high approximately 200ms after crossing the threshold.
During power-down, RESET goes LOW as VCC falls below the
threshold level and is guaranteed to be under 0.4V with VCC
above 1.2V.
In a brownout situation where VCC falls below the threshold
level, RESET pulses low. If a brownout occurs during an alreadyinitiated reset, the pulse will continue for a minimum of 140ms.
Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point
and uncommitted output (PFO) and noninverting input (PFI).
This comparator can be used as a supply voltage monitor with an
external resistor voltage divider. The attenuated voltage at PFI
should be set just below the 1.25 threshold. As the supply level
falls, PFI is reduced causing the PFO output to transit LOW.
Normally PFO interrupts the processor so the system can be shut
down in a controlled manner.
5V
VCC
0V
By connecting the watchdog output (WDO) and MR, a watchdog
timeout forces RESET to be generated. The IMP813L should be
used when an active-HIGH RESET is required.
Watchdog Timer
The watchdog timer available on the IMP705/706/813L monitors
µP/µC activity. If activity is not detected within 1.6 seconds, the
internal timer puts the watchdog output, WDO, into a LOW
state. WDO will remain LOW until activity is detected at WDI.
The watchdog function is disabled, meaning it is cleared and not
counting, if WDI is floated or connected to a three-stated circuit.
The watchdog timer is also disabled if RESET is asserted. When
RESET becomes inactive and the WDI input sees a high or low
transition as short as 50ns, the watchdog timer will begin a 1.6
second countdown. Additional transitions at WDI will reset the
watchdog timer and initiate a new countdown sequence.
WDO will also become LOW and remain so, whenever the
supply voltage, VCC , falls below the device threshold level. WDO
goes HIGH as soon as VCC transitions above the threshold. There
is no minimum pulse width for WDO as there is for the RESET
outputs. If WDI is floated, WDO essentially acts as a low-power
output indicator.
5V
vRT
WDI
tRS
0V
tRS
tWD
tWD
tWP
5V
5V
RESET
WDO
0V
0V
5V
MR
0V
tWD
5V
MR extermally
set low
RESET
0V
tMD
RESET triggered by MR
tRS
tMR
5V
5V
(RESET)
IMP813L 0V
WDO
0V
705_05.eps
705_04.eps
Figure 1. WDI Three-state operation
© 1999 IMP, Inc.
Figure 2. Watchdog Timing
408-432-9100/www.impweb.com
5
IMP705/6/7/8, 8 13L
Application Information
Ensuring That RESET is Valid Down to VCC = 0V
Bi-directional Reset Pin Interfacing
When VCC falls below 1.1V, the IMP705-708 RESET output no
longer pulls down; it becomes indeterminate. To avoid the possibility that stray charges build up and force RESET to the wrong
state, a pull-down resistor should be connected to the RESET pin,
thus draining such charges to ground and holding RESET
low. The resistor value is not critical. A 100kΩ resistor will pull
RESET to ground without loading it.
The IMP705/6/7/8 can interface with µP/µC bi-directional reset
pins by connecting a 4.7kΩ resistor in series with the RESET
output and the µP/µC bi-directional RESET pin.
BUF
Buffered
RESET
VCC < 1.1V
VCC
VCC
IMP70x
IMP70x
Power
Supply
µC or µP
4.7kΩ
100kW
RESET
RESET
RESET
Input
GND
GND
GND
Bi-directional I/O Pin
(Example: 68HC11)
705_08.eps
705_06.eps
Figure 3. Ensuring That RESET is Valid Down to VCC = 0V
6
Figure 3. Bi-directional Reset Pin Interfacing
408-432-9100/www.impweb.com
© 1999 IMP, Inc.
IMP705/6/7/8, 8 13L
Application Information
Monitoring Voltages Other Than VCC
Monitoring a Negative Voltage
The IMP705-708 can monitor voltages other than VCC using the
Power Fail circuitry. If a resistive divider is connected from the
voltage to be monitored to the Power Fail input, PFI, the PFO
(output) will go LOW if the divider voltage goes below its 1.25V
reference. Should hysteresis be desired, connect a resistor (equal
to approximately 10 times the sum of the two resistors in the
divider) between the PFI and PFO pins. A capacitor between PFI
and GND will reduce circuit sensitivity to input high-frequency
noise. If it is desired to assert a RESET in addition to the PFO flag,
this may be achieved by connecting the PFO output to MR.
The Power-Fail circuitry can also monitor a negative supply rail.
When the negative rail is OK, PFO will be LOW, and when the
negative rail is failing (not negative enough), PFO goes HIGH
(the opposite of when positive voltages are monitored). To trigger
a reset, these outputs need to be inverted: adding the resistors
and transistor as shown achieves this. The RESET output will
then have the same sense as for positive voltages: good = HIGH,
bad = LOW. It should be noted that this circuit’s accuracy depends
on the VCC line, the PFI threshold tolerance, and the resistors.
+5V
+
VCC = 5V
VCC
VIN = 12V
MR
MR
IMP70x
IMP70x
PFO
1MW
PFI
130kW
VCC
RESET
GND
PFI
To Processor
12V Threshold
~10.87V
705_07.eps
Figure 4. Monitoring Voltages Other Than VCC
© 1999 IMP, Inc.
PFO
RP
RN
RESET
GND
5 − 1.25 1.25 − VTRIP
=
RP
RN
—
Negative Input
Voltage
705_09.eps
Figure 5. Monitoring a Negative Voltage
408-432-9100/www.impweb.com
7
IMP705/6/7/8, 8 13L
Package Dimensions
Plastic DIP (8-Pin)*
Inches
Min
D1
D
0.210
––––
5.33
0.015
–––––
0.38
–––––
A2
0.115
0.195
2.92
4.95
b
0.014
0.022
0.36
0.56
b2
0.045
0.070
1.14
1.78
b3
0.030
0.045
0.80
1.14
D
0.355
0.400
9.02
10.16
D1
0.005
–––––
0.13
–––––
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
0.100
–––––
2.54
eA
0.300
–––––
7.62
eB
–––––
0.430
eC
–––––
0.060
L
0.115
0.150
C
b2
eA
eB
b
–––––
A1
E
0°–15°
e
A
E1
A A2
L A1
Millimeters
Max
Min
Max
Plastic DIP (8-Pin)
Plastic DIP (8-Pin)a.eps
MicroSO (8-Pin)**
a
–––––
10.92
2.92
3.81
MicroSO (8-Pin)
+
E1 E
L
D
–––––
0.0433
––––
1.10
A1
0.0020
0.0059
0.050
0.15
A2
0.0295
0.0374
0.75
0.95
b
0.0098
0.0157
0.25
0.40
C
0.0051
0.0091
0.13
0.23
D
0.1142
0.1220
2.90
e
C
A2
A
0.0256 BSC
E
D
A
e
0.10mm
0.004in
MicroSO (8-Pin).eps
A1
b
0.193 BSC
4.90 BSC
E1
0.1142
0.1220
2.90
3.10
L
0.0157
0.0276
0.40
0.70
a
0°
6°
0°
6°
0.053
0.069
SO (8-Pin)
SO (8-Pin)***
A
0°– 8°
L
H
C
D
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
e
E
3.10
0.65 BSC
0.050
1.27
E
0.150
0.157
3.80
4.00
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
D
0.189
0.197
4.80
5.00
* JEDEC Drawing MS-001BA
** JEDEC Drawing MO-187AA
*** JEDEC Drawing MS-012AA
A
e
B
8
A1
SO (8-Pin).eps
408-432-9100/www.impweb.com
© 1999 IMP, Inc.
IMP705/6/7/8, 8 13L
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Tel: 800-438-3722
Fax: 408-434-0335
e-mail: [email protected]
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
© 1999 IMP, Inc.
Printed in USA
Publication #: 1017
Revision:
A
Issue Date:
08/17/99
Type:
Preliminary
Similar pages