IK Semicon IN74HCT164AD 8-bit serial-input/parallel-output shift resister high-performance silicon-gate cmo Datasheet

TECHNICAL DATA
IN74HCT164A
8-BIT SERIAL-INPUT/PARALLEL-OUTPUT
SHIFT RESISTER
High-Performance Silicon-Gate CMOS
The IN74HCT164A may be used as a level converter for
interfacing TTL or NMOS outputs to high-speed CMOS inputs.
The IN74HCT164A is identical in pin out to the LS/ALS164.
•
•
•
•
TTL/NMOS-Compatible Input Levels.
Outputs Directly Interface to CMOS, NMOS and TTL.
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HCT164AN Plastic
IN74HCT164AD SOIC
TA = -55° to 125° C for all
packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
PIN 14 =VCC
PIN 7 = GND
Reset
L
H
H
H
Inputs
Clock
X
A1
X
X
H
D
A2
X
X
D
H
Outputs
QA QB ... QH
L L ... L
no change
D QAn ... QGn
D QAn ... QGn
D = data input
X = don’t care
QAn - QGn = data shifted from the previous stage
on a rising edge at the clock input.
Rev. 00
IN74HCT164A
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
Parameter
Value
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
DC Input Current, per Pin
±20
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
Power Dissipation in Still Air, Plastic DIP+
750
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
TL
Lead Temperature, 1 mm from Case for 10
260
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from -55° to 125°C
SOIC Package: : - 7 mW/°C from -55° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
TA
t r, t f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
VCC
+125
500
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or
electric fields. However, precautions must be taken to avoid applications of any voltage higher than
maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be
constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
Rev. 00
IN74HCT164A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VC
Guaranteed Limit
C
≤85
°C
≤125
°C
Unit
4.5
5.5
25 °C
to
-55°C
2.0
2.0
2.0
2.0
2.0
2.0
V
V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
or
VIN=VIH
⎢IOUT⎢ ≤ 20 µA
VIL
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
VIN=VIH
or
⎢IOUT⎢ ≤ 4.0 mA
Low- VIN=VIH
Output ⎢IOUT⎢ ≤ 20 µA
VIL
4.5
4.5
5.5
3.98
0.1
0.1
3.84
0.1
0.1
3.7
0.1
0.1
4.5
5.5
0.26
±0.1
0.33
±1.0
0.4
±1.0
µA
5.5
1.0
10
40
µA
≥-55°C
25°C to
125°C
mA
2.9
2.4
Symbol
Parameter
Test Conditions
V
VIH
Minimum
HighLevel
Input
Voltage
Maximum Low Level
Input
Voltage
Minimum
HighLevel
Output
Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
VCC-0.1
VOUT=
⎢IOUT⎢ ≤ 20 µA
VIL
VOH
VOL
IIN
ICC
∆ICC
Maximum
Level
Voltage
VIN=VIH
⎢IOUT⎢ ≤ 4.0 mA
Maximum
Input VIN=VCC or GND
Leakage Current
Maximum
or
GND
VIN=VCC
Quiescent Supply IOUT=0µA
Current
(per Package)
Additional
VIN = 2.4 V, Any One
Quiescent Supply Input
Current
VIN=VCC or GND, Other
Inputs
IOUT=0µA
5.5
V
Rev. 00
IN74HCT164A
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=6.0 ns)
Symbol
Parameter
fmax
Maximum Clock Frequency (50% Duty
Cycle) (Figures 1 and 4)
Maximum Propagation Delay,Clock to Q
(Figures 1 and 4)
Maximum Propagation Delay,Reset to Q
(Figures 2 and 4)
Maximum Output Transition Time, Any
Output (Figures 1 and 4)
Maximum Input Capacitance
tPLH, tPHL
tPHL
tTLH, tTHL
CIN
CPD
Power Dissipation Capacitance (Per Package)
Used to determine the no-load dynamic
power
consumption:
PD=CPDVCC2f+ICCVCC
Guaranteed Limit
25 °C ≤85°C
≤125
to
°C
-55°C
30
24
20
Unit
MHz
38
48
58
ns
41
52
63
ns
15
19
22
ns
10
pF
Typical @25°C,VCC=5.0 V
360
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
tSU
Minimum Setup Time,A1
or A2 to Clock (Figure 3)
Minimum Hold Time,
Clock to A1 or A2 (Figure
3)
Minimum Recovery Time,
Reset Inactive to Clock
(Figure 2)
Minimum Pulse Width,
Reset (Figure 2)
Minimum Pulse Width,
Clock (Figure 1)
th
trec
tw
tw
Guaranteed Limit
25 °C to
≤85°C
≤125°C
-55°C
7
8
9
Unit
ns
5
5
5
ns
5
5
5
ns
12
15
20
ns
12
15
20
ns
Rev. 00
IN74HCT164A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
Rev. 00
IN74HCT164A
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
8
14
B
7
1
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
N
G
M
K
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
H
B
1
G
P
7
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
8.55
8.75
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.27
J
0°
8°
K
0.1
0.25
M
0.19
0.25
P
5.8
6.2
R
0.25
0.5
Rev. 00
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