NXP IP4770CZ16 Vga/video interface with integrated buffers, esd protection and integrated termination resistor Datasheet

IP4770/71/72CZ16
VGA/video interface with integrated buffers, ESD protection
and integrated termination resistors
Rev. 01 — 25 October 2006
Product data sheet
1. General description
The IP4770CZ16, IP4771CZ16, IP4772CZ16 is connected between the VGA/DVI
interface and the video graphics controller and includes level shifting for the DDC signals,
buffering for the SYNC lines as well as high-level ESD protection diodes for the RGB
signal lines.
The level shifting functions are required when the DDC controller operates at a lower
supply voltage than the monitor. To use this level shifting function the gates of the two
N-channel MOSFETs have to be connected to the supply rail of the DDC transceivers.
Buffering for the SYNC signals is provided by two non-inverting buffers, which accept TTL
input levels and convert these to CMOS compliant output levels between pins VCC(SYNC)
and GND.
The IP4770CZ16 and IP4771CZ16 contain the formerly external termination resistors,
which are typically required for the HSYNC and VSYNC lines of the video interface:
• IP4770CZ16: Rsync = 55 Ω
• IP4771CZ16: Rsync = 65 Ω
• IP4772CZ16: Rsync =10 Ω to allow termination of the SYNC lines
All RGB I/Os are protected by a special diode configuration offering a low line capacitance
of 4 pF (maximum) only to provide protection to downstream components for ESD
voltages as high as ±8 kV contact discharge according to IEC 61000-4-2, level 4 standard.
2. Features
n Integrated high-level ESD protection, buffering, SYNC signal impedance matching and
level shifting
n Terminal connections with integrated rail-to-rail clamping diodes with downstream ESD
protection of ±8 kV according to IEC 61000-4-2, level 4 standard
n Backflow protection on DDC lines
n Drivers for HSYNC and VSYNC lines
n Bidirectional level shifting N-channel FETs available for DDC clock and DDC data
channels
n Integrated impedance matching resistors on SYNC lines
n Line capacitance < 4 pF per channel
n Lead-free package and RoHS compliant
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
3. Applications
n To terminate and to buffer channels, to reduce EMI/RFI and to provide downstream
ESD protection for:
u VGA interfaces including DDC channels
u Desktop and notebooks PCs
u Graphics cards
u Set top boxes
4. Ordering information
Table 1.
Ordering information
Type number
IP4770CZ16
Package
Name
Description
Version
SSOP16
plastic shrink small outline package; 16 leads; body
width 3.9 mm; lead pitch 0.635 mm
SOT519-1
IP4771CZ16
IP4772CZ16
5. Functional diagram
VCC(VIDEO)
VCC(SYNC)
Rterm
SYNC_OUT1
SYNC_IN1
VIDEO_1
VIDEO_2
Rterm
SYNC_IN2
SYNC_OUT2
VIDEO_3
DDC_OUT1
DDC_OUT2
VCC(SYNC)
BYP
VCC(DDC)
DDC_IN1
DDC_IN2
001aae818
IP4772CZ16: Rsync = Rbuffer and Rterm = 0 Ω.
Fig 1. Functional diagram
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
2 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
6. Pinning information
6.1 Pinning
VCC(SYNC)
1
16 SYNC_OUT2
VCC(VIDEO)
2
15 SYNC_IN2
VIDEO_1
3
VIDEO_2
4
VIDEO_3
5
GND
6
11 DDC_IN2
VCC(DCC)
7
10 DDC_IN1
BYP
8
14 SYNC_OUT1
IP4770CZ16
IP4771CZ16
IP4772CZ16
13 SYNC_IN1
12 DDC_OUT2
9
DDC_OUT1
001aae809
Fig 2. Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin Description
VCC(SYNC)
1
supply voltage for SYNC_1 and SYNC_2 level shifter and their connected
ESD protections
VCC(VIDEO)
2
supply voltage for VIDEO_1, VIDEO_2 and VIDEO_3 protection circuits
VIDEO_1
3
video signal ESD protection channel 1
VIDEO_2
4
video signal ESD protection channel 2
VIDEO_3
5
video signal ESD protection channel 3
GND
6
ground
VCC(DDC)
7
supply voltage for DDC_1 and DDC_2 level shifter N-FET gates
BYP
8
this input is used to connect an external 0.2 µF bypass capacitor to increase
ESD withstand voltage rating for the DDC outputs (±8 kV with capacitor or
±4 kV without capacitor)
DDC_OUT1
9
DDC signal output 1; connected to the video connector side of one of the
SYNC lines
DDC_IN1
10
DDC signal input 1; connected to the VGA controller side of one of the SYNC
lines
DDC_IN2
11
DDC signal input 2; connected to the VGA controller side of one of the SYNC
lines
DDC_OUT2
12
DDC signal output 2; connected to the video connector side of one of the
SYNC lines
SYNC_IN1
13
SYNC signal input 1; connected to the VGA controller side of one of the
SYNC lines
SYNC_OUT1 14
SYNC signal output 1; connected to the video connector side of one of the
SYNC lines
SYNC_IN2
SYNC signal input 2; connected to the VGA controller side of one of the
SYNC lines
15
SYNC_OUT2 16
SYNC signal output 2; connected to the video connector side of one of the
SYNC lines
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
3 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to ground (GND).
Symbol
VESD
Parameter
Conditions
electrostatic discharge voltage
Min
Max
Unit
level 4; contact
−8
+8
kV
level 4; air discharge
−15
+15
kV
level 1; contact
−2
+2
kV
level 1; air discharge
−2
+2
kV
IEC 61000-4-2; pins
VIDEO_1, VIDEO_2,
VIDEO_3, SYNC_OUT1,
SYNC_OUT2,
DDC_OUT1, DDC_OUT2
[1]
IEC 61000-4-2; all other
pins
VCC(VIDEO)
video supply voltage
−0.5
5.5
V
VCC(DDC)
data display channel supply voltage
−0.5
5.5
V
VCC(SYNC)
synchronization supply voltage
−0.5
5.5
V
VI(VIDEO_1)
input voltage on pin VIDEO_1
−0.5
VCC(VIDEO)
V
VI(VIDEO_2)
input voltage on pin VIDEO_2
−0.5
VCC(VIDEO)
V
VI(VIDEO_3)
input voltage on pin VIDEO_3
−0.5
VCC(VIDEO)
V
VI(DDC_IN1)
input voltage on pin DDC_IN1
−0.5
VCC(DDC)
V
VI(DDC_IN2)
input voltage on pin DDC_IN2
−0.5
VCC(DDC)
V
VI(SYNC_IN1)
input voltage on pin SYNC_IN1
−0.5
VCC(SYNC)
V
VI(SYNC_IN2)
input voltage on pin SYNC_IN2
−0.5
VCC(SYNC)
V
VO(DDC_OUT1)
output voltage on pin DDC_OUT1
−0.5
VCC(DDC)
V
VO(DDC_OUT2)
output voltage on pin DDC_OUT2
−0.5
VCC(DDC)
V
Ptot
total power dissipation
-
500
mW
Tstg
storage temperature
−55
+125
°C
[1]
Tamb = 25 °C
Pins BYP, VCC(VIDEO) and VCC(SYNC) must be bypassed to ground (pin GND) via a low-impedance ground plane with 0.22 µF, low
inductance, chip ceramic capacitor at each supply pin.
ESD pulse is applied between the pins VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1, DDC_OUT2 and
GND.
The bypass capacitor at pin BYP can be omitted. In this case the maximum ESD level for DDC_OUT1 and DDC_OUT2 pins is reduced
to ±4 kV.
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
4 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
8. Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol
Parameter
Toper
operating temperature
Conditions
Min
Typ
Max
Unit
−40
-
+85
°C
Min
Typ
Max
Unit
[1]
-
-
50
µA
[1]
-
-
2
mA
9. Characteristics
Table 5.
Sync circuit characteristics
VCC(SYNC) = 5 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Supply: pin VCC(SYNC)
ICC(SYNC)
supply current on pin VCC(SYNC)
SYNC input at 3 V
Input: pins SYNC_IN1 and SYNC_IN2
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.6
V
Output: pins SYNC_OUT1 and SYNC_OUT2
VOH
HIGH-level output voltage
IOH = 1 mA
4.85
-
-
V
IP4772CZ16; IOH = 24 mA
2.0
-
-
V
VOL
LOW-level output voltage
IOL = 1 mA
-
-
0.15
V
IP4772CZ16; IOL = 24 mA
-
-
0.8
V
IP4770CZ16
[2]
-
55
-
Ω
IP4771CZ16
[2]
-
65
-
Ω
IP4772CZ16
[3]
-
10
-
Ω
LOW-to-HIGH propagation delay
CL = 50 pF; tr and tf ≤ 5 ns
[4]
-
-
12
ns
tPHL
HIGH-to-LOW propagation delay
CL = 50 pF; tr and tf ≤ 5 ns
[4]
-
-
12
ns
tr(o)
output rise time
CL = 50 pF; tr and tf ≤ 5 ns
-
4
-
ns
CL = 7 pF; tr and tf ≤ 5 ns
-
1.5
-
ns
CL = 50 pF; tr and tf ≤ 5 ns
-
4
-
ns
CL = 7 pF; tr and tf ≤ 5 ns
-
1.5
-
ns
Rsync
synchronization resistance
Sync channel
tPLH
output fall time
tf(o)
Protection diode
IL(r)
reverse leakage current
per channel; V = 3.0 V
-
-
1
µA
VBRzd
Zener diode breakdown voltage
I = 1 mA
6
-
9
V
VFd
diode forward voltage
IF = 1 mA
-
0.7
-
V
[1]
SYNC outputs unloaded.
[2]
Rsync = Rterm + Rbuffer.
[3]
Rsync = Rbuffer because Rterm = 0 Ω.
[4]
This parameter is guaranteed by design and characterization.
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
5 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
Table 6.
Video circuit characteristics
VCC(VIDEO) = 5 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
static input signals
-
-
10
µA
-
-
4
pF
Supply: pin VCC(VIDEO)
ICC(VIDEO)
supply current on pin VCC(VIDEO)
Video channel: pins VIDEO_1, VIDEO_2 and VIDEO_3
[1]
Cch(video)
video channel capacitance
fi = 1 MHz; VI = 2.5 V
Ii(video)
video input current
VI = VCC(VIDEO) or GND
−1
-
+1
µA
IF = 1 mA
-
0.7
-
V
Protection diode
diode forward voltage
VFd
[1]
This parameter is guaranteed by design and characterization.
Table 7.
Level circuit characteristics
VCC(DDC) = 5 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ
Max
Unit
-
-
10
µA
-
-
10
µA
VCC(DDC) = 2.5 V; VS = GND;
IDS = 3 mA
-
-
0.18
V
per channel; V = 3.0 V
-
-
1
µA
Supply: pin VCC(DDC)
ICC(DDC)
supply current on pin VCC(DDC)
N-MOSFET
IL(off)
off-state leakage current
∆Von
on-state voltage drop
[1]
Protection diode
IL(r)
reverse leakage current
VBRzd
Zener diode breakdown voltage
I = 1 mA
6
-
9
V
VFd
diode forward voltage
IF = 1 mA
-
0.7
-
V
[1]
Input VI(DDC_INx) ≤ VCC(DDC)− 0.4 V and output VO(DDC_OUTx) = VCC(DDC) or
input VI(DDC_INx) = VCC(DDC) and output VO(DCC_OUTx) ≤ VCC(DCC) − 0.4 V.
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
6 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
10. Application information
The IP4770CZ16, IP4771CZ16, IP4772CZ16 should be placed as close as possible to the
VGA/DVI interface connector.
The ESD protection channels VIDEO_1, VIDEO_2 and VIDEO_3 can be connected in
any order with RBG signals.
The 100 kΩ resistors between the DDC_OUTx channels and VCC_5V are optional. They
may be used, if required, to pull-up the DDC_OUTx lines to VCC_5V when no monitor is
connected to the VGA connector. Backflow current can flow between pins DDC_OUTx
and VCC_5V via these resistors when VCC_5V is powered down.
HSYNC
VSYNC
100 kΩ
100 kΩ
EMI-filter
VCC(SYNC)
VCC_5V
SYNC_OUT2
VSYNC_OUT
SYNC_IN2
VCC(DCC)
VCCGPIO
SYNC_GND
SYNC_IN1
SYNC_OUT1
HSYNC_OUT
VCC(VIDEO)
VCCA_DAC
RED
FILTER
VIDEO_1
GREEN
FILTER
VIDEO_2
DCC_OUT2
DDC_DATA
DCC_IN2
DIG_GND
DCC_IN1
BLUE
FILTER
VIDEO_3
DCC_OUT1
DDC_CLK
3 × 75 Ω
IP4770CZ16
IP4771CZ16
IP4772CZ16
RED_VIDEO
GREEN_VIDEO
BLUE_VIDEO
DDC_CLK
RED_GND
DDC_DATA
GREEN_GND
BLUE_GND
001aae819
Fig 3. Application diagram
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
7 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
11. Package outline
SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm
D
E
SOT519-1
A
X
c
y
HE
v M A
Z
9
16
A2
A
(A 3)
A1
θ
Lp
L
8
1
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.73
0.25
0.10
1.55
1.40
0.25
0.31
0.20
0.25
0.18
5.0
4.8
4.0
3.8
0.635
6.2
5.8
1
0.89
0.41
0.2
0.18
0.09
0.18
0.05
8o
o
0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-05-04
03-02-18
SOT519-1
Fig 4. Package outline SOT519-1 (SSOP16)
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
8 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
12. Abbreviations
Table 8.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DDC
Data Display Channel
DVI
Digital Video Interface
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
FET
Field Effect Transistor
HSYNC
Horizontal SYNChronization
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
PC
Personal Computer
RFI
Radio Frequency Interference
RGB
Red Green Blue
SYNC
SYNChronization
TTL
Transistor-Transistor Logic
VGA
Video Graphics Adapter
VSYNC
Vertical SYNChronization
13. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
IP4770CZ16_4771_4772_1
20061025
Product data sheet
-
-
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
9 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
IP4770CZ16_4771_4772_1
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 01 — 25 October 2006
10 of 11
IP4770/71/72CZ16
NXP Semiconductors
VGA/video interface with ESD protection
16. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Application information. . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Contact information. . . . . . . . . . . . . . . . . . . . . 10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 October 2006
Document identifier: IP4770CZ16_4771_4772_1
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