Infineon IPD13N03LA Optimos 2 power-transistor Datasheet

OptiMOS®2 Power-Transistor
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Product Summary
Features
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target applications
V DS
25
V
R DS(on),max
12.8
mΩ
ID
30
A
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
• Superior thermal resistance
• 175 °C operating temperature
Type
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Package
P-TO252-3-11
P-TO252-3-23
P-TO251-3-11
P-TO251-3-21
Ordering Code
Q67042-S4159
Q67042-S4195
Q67042-S4248
Q67042-S4160
Marking
13N03LA
13N03LA
13N03LA
13N03LA
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol Conditions
Continuous drain current
ID
Value
T C=25 °C2)
30
T C=100 °C
30
Unit
A
Pulsed drain current
I D,pulse
T C=25 °C3)
210
Avalanche energy, single pulse
E AS
I D=24 A, R GS=25 Ω
60
mJ
Reverse diode dv /dt
dv /dt
I D=30 A, V DS=20 V,
di /dt =200 A/µs,
T j,max=175 °C
6
kV/µs
Gate source voltage4)
V GS
Power dissipation
P tot
Operating and storage temperature
T j, T stg
T C=25 °C
IEC climatic category; DIN IEC 68-1
Rev. 1.7
±20
V
46
W
-55 ... 175
°C
55/175/56
page 1
2004-05-24
Parameter
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Values
Symbol Conditions
Unit
min.
typ.
max.
minimal footprint
-
-
3.2
75
6 cm2 cooling area5)
-
-
50
25
-
-
Thermal characteristics
Thermal resistance, junction - case
SMD version, device on PCB
R thJC
R thJA
K/W
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V (BR)DSS V GS=0 V, I D=1 mA
Gate threshold voltage
V GS(th)
V DS=V GS, I D=20 µA
1.2
1.6
2
Zero gate voltage drain current
I DSS
V DS=25 V, V GS=0 V,
T j=25 °C
-
0.1
1
V DS=25 V, V GS=0 V,
T j=125 °C
-
10
100
V
µA
Gate-source leakage current
I GSS
V GS=20 V, V DS=0 V
-
10
100
nA
Drain-source on-state resistance
R DS(on)
V GS=4.5 V, I D=20 A
-
17.5
21.9
mΩ
V GS=10 V, I D=30 A
-
10.7
12.8
-
0.9
-
Ω
18
36
-
S
Gate resistance
RG
Transconductance
g fs
|V DS|>2|I D|R DS(on)max,
I D=30 A
1)
J-STD20 and JESD22
2)
Current is limited by bondwire; with an R thJC=3.2 K/W the chip is able to carry 47 A.
3)
See figure 3
4)
T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.7
page 2
2004-05-24
Parameter
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Values
Symbol Conditions
Unit
min.
typ.
max.
-
784
303
1043
402
-
41
62
-
5.4
8.0
-
4.6
6.9
-
15
23
Dynamic characteristics
Input capacitance
Output capacitance
C iss
C oss
Reverse transfer capacitance
Crss
Turn-on delay time
t d(on)
Rise time
tr
Turn-off delay time
t d(off)
Fall time
tf
-
2.6
3.9
Gate to source charge
Q gs
-
2.7
3.6
Gate charge at threshold
Q g(th)
-
1.3
1.7
Gate to drain charge
Q gd
-
1.8
2.7
Switching charge
Q sw
-
3.3
4.7
Gate charge total
Qg
-
6.3
8.3
Gate plateau voltage
V plateau
-
3.4
-
Gate charge total, sync. FET
Q g(sync)
V DS=0.1 V,
V GS=0 to 5 V
-
5.5
7.3
Output charge
Q oss
V DD=15 V, V GS=0 V
-
6.6
8.7
-
-
30
-
-
210
V GS=0 V, V DS=15 V,
f =1 MHz
V DD=15 V, V GS=10 V,
I D=15 A, R G=2.7 Ω
pF
ns
Gate Charge Characteristics 6)
V DD=15 V, I D=15 A,
V GS=0 to 5 V
nC
V
nC
Reverse Diode
Diode continous forward current
IS
Diode pulse current
I S,pulse
Diode forward voltage
V SD
V GS=0 V, I F=30 A,
T j=25 °C
-
0.95
1.2
V
Reverse recovery charge
Q rr
V R=15 V, I F=I S,
di F/dt =400 A/µs
-
-
10
nC
6)
Rev. 1.7
T C=25 °C
A
See figure 16 for gate charge parameter definition
page 3
2004-05-24
1 Power dissipation
2 Drain current
P tot=f(T C)
I D=f(T C); V GS≥10 V
50
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
40
40
30
I D [A]
P tot [W]
30
20
20
10
10
0
0
0
50
100
150
200
0
50
100
T C [°C]
150
3 Safe operating area
4 Max. transient thermal impedance
I D=f(V DS); T C=25 °C; D =0
Z thJC=f(t p)
parameter: t p
parameter: D =t p/T
1000
10
1 µs
limited by on-state
resistance
0.5
100
1
0.2
Z thJC [K/W]
I D [A]
10 µs
100 µs
DC
10
0.1
0.05
0.02
0.1
1 ms
0.01
single pulse
10 ms
1
0.1
1
10
100
V DS [V]
Rev. 1.7
200
T C [°C]
0.01
0
0
0
0
0
0
1
10-6
10-5
10-4
10-3
10-2
10-1
100
t p [s]
page 4
2004-05-24
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
5 Typ. output characteristics
6 Typ. drain-source on resistance
I D=f(V DS); T j=25 °C
R DS(on)=f(I D); T j=25 °C
parameter: V GS
parameter: V GS
60
50
10 V
3V
4.5 V
50
3.5 V
4.1 V
3.8 V
3.2 V
40
R DS(on) [mΩ]
40
I D [A]
4.1 V
30
3.8 V
30
4.5 V
20
20
3.5 V
10 V
10
10
3.2 V
3V
2.8 V
0
0
0
1
2
3
0
10
20
V DS [V]
30
40
50
I D [A]
7 Typ. transfer characteristics
8 Typ. forward transconductance
I D=f(V GS); |V DS|>2|I D|R DS(on)max
g fs=f(I D); T j=25 °C
parameter: T j
60
50
40
40
I D [A]
g fs [S]
30
20
20
10
175 °C
25 °C
0
0
0
1
2
3
4
5
Rev. 1.7
0
10
20
30
40
50
60
I D [A]
V GS [V]
page 5
2004-05-24
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
R DS(on)=f(T j); I D=30 A; V GS=10 V
V GS(th)=f(T j); V GS=V DS
parameter: I D
24
2.5
20
2
200 µA
98 %
12
1.5
V GS(th) [V]
R DS(on) [mΩ]
16
typ
20 µA
1
8
0.5
4
0
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
T j [°C]
T j [°C]
11 Typ. Capacitances
12 Forward characteristics of reverse diode
C =f(V DS); V GS=0 V; f =1 MHz
I F=f(V SD)
parameter: T j
104
1000
10000
25 °C
Ciss
1000
C [pF]
103
100
175 °C, 98%
I F [A]
Coss
175 °C
25 °C, 98%
102
10
100
Crss
101
1
10
0
5
10
15
20
25
30
V DS [V]
Rev. 1.7
0.0
0.5
1.0
1.5
2.0
V SD [V]
page 6
2004-05-24
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
13 Avalanche characteristics
14 Typ. gate charge
I AS=f(t AV); R GS=25 Ω
V GS=f(Q gate); I D=25 A pulsed
parameter: T j(start)
parameter: V DD
100
12
15 V
10
20 V
8
V GS [V]
I AV [A]
5V
25 °C
100 °C
150 °C
10
6
4
2
1
0
1
10
100
1000
0
2
4
6
8
10
12
14
Q gate [nC]
t AV [µs]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V BR(DSS)=f(T j); I D=1 mA
29
V GS
28
Qg
27
V BR(DSS) [V]
26
25
24
V g s(th)
23
22
Q g(th)
21
Q sw
Q gs
20
-60
-20
20
60
100
140
Q g ate
Q gd
180
T j [°C]
Rev. 1.7
page 7
2004-05-24
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Package Outline
P-TO252-3-11: Outline
Footprint:
Packaging:
Dimensions in mm
Rev. 1.7
page 8
2004-05-24
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Package Outline
P-TO252-3-23: Outline
Footprint:
Dimensions in inch [mm]
Rev. 1.7
page 9
2004-05-24
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Package Outline
P-TO251-3-11: Outline
P-TO251-3-21: Outline
Dimensions in inch [mm]
Rev. 1.7
page 10
2004-05-24
IPD13N03LA
IPF13N03LA
IPS13N03LA
IPU13N03LA
Published by
Infineon Technologies AG
Bereich Kommunikation
St.-Martin-Straße 53
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
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We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
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For further information on technology, delivery terms and conditions and prices, please contact your
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(see address list).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact your nearest Infineon Technologies office.
Infineon Technologies' components may only be used in life-support devices or systems with the
expressed written approval of Infineon Technologies if a failure of such components can reasonably
be expected to cause the failure of that life-support device or system, or to affect the safety or
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in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,
it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.7
page 11
2004-05-24
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