Infineon IPDH5N03LAG Optimosâ®2 power-transistor Datasheet

IPDH5N03LA G
OptiMOS®2 Power-Transistor
IPSH5N03LA G
Product Summary
Features
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target application
V DS
25
V
R DS(on),max (SMD version)
5.2
mΩ
ID
50
A
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
• Superior thermal resistance
• 175 °C operating temperature
• Pb-free lead plating; RoHS compliant
Type
IPDH5N03LA
IPSH5N03LA
Package
P-TO252-3-11
P-TO251-3-11
Marking
H5N03LA
H5N03LA
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol Conditions
Continuous drain current
ID
Value
T C=25 °C2)
50
T C=100 °C
50
Pulsed drain current
I D,pulse
T C=25 °C3)
350
Avalanche energy, single pulse
E AS
I D=45 A, R GS=25 Ω
225
Reverse diode dv /dt
dv /dt
I D=50 A, V DS=20 V,
di /dt =200 A/µs,
T j,max=175 °C
6
Gate source voltage4)
V GS
Power dissipation
P tot
Operating and storage temperature
T j, T stg
T C=25 °C
IEC climatic category; DIN IEC 68-1
Rev. 1.3
Unit
A
mJ
kV/µs
±20
V
83
W
-55 ... 175
°C
55/175/56
page 1
2006-05-11
IPDH5N03LA G
Parameter
IPSH5N03LA G
Values
Symbol Conditions
Unit
min.
typ.
max.
-
-
1.8
minimal footprint
-
-
75
6 cm2 cooling area5)
-
-
50
25
-
-
Thermal characteristics
Thermal resistance, junction - case
R thJC
SMD version, device on PCB
R thJA
K/W
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V (BR)DSS V GS=0 V, I D=1 mA
Gate threshold voltage
V GS(th)
V DS=V GS, I D=35 µA
1.2
1.6
2
Zero gate voltage drain current
I DSS
V DS=25 V, V GS=0 V,
T j=25 °C
-
0.1
1
V DS=25 V, V GS=0 V,
T j=125 °C
-
10
100
V
µA
Gate-source leakage current
I GSS
V GS=20 V, V DS=0 V
-
10
100
nA
Drain-source on-state resistance
R DS(on)
V GS=4.5 V, I D=30 A
-
7.0
8.7
mΩ
V GS=4.5 V, I D=30 A,
SMD version
-
6.8
8.5
V GS=10 V, I D=50 A
-
4.5
5.4
V GS=10 V, I D=50 A,
SMD version
-
4.3
5.2
-
1
-
Ω
38
76
-
S
Gate resistance
RG
Transconductance
g fs
|V DS|>2|I D|R DS(on)max,
I D=50 A
1)
J-STD20 and JESD22
2)
Current is limited by bondwire; with an R thJC=1.8 K/W the chip is able to carry 94 A.
3)
See figure 3
4)
T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.3
page 2
2006-05-11
IPDH5N03LA G
Parameter
IPSH5N03LA G
Values
Symbol Conditions
Unit
min.
typ.
max.
-
2093
2653
-
800
1064
Dynamic characteristics
Input capacitance
C iss
Output capacitance
C oss
Reverse transfer capacitance
Crss
-
98
147
Turn-on delay time
t d(on)
-
10
14
Rise time
tr
-
7.2
11
Turn-off delay time
t d(off)
-
29
43
Fall time
tf
-
4.6
6.9
Gate to source charge
Q gs
-
6.7
9.0
Gate charge at threshold
Q g(th)
-
3.3
4.2
Gate to drain charge
Q gd
-
4.6
6.9
Switching charge
Q sw
-
8.0
11
Gate charge total
Qg
-
17
22
Gate plateau voltage
V plateau
-
3.2
-
Gate charge total, sync. FET
Q g(sync)
V DS=0.1 V,
V GS=0 to 5 V
-
15
19
Output charge
Q oss
V DD=15 V, V GS=0 V
-
17
23
-
-
50
-
-
350
V GS=0 V, V DS=15 V,
f =1 MHz
V DD=15 V, V GS=10 V,
I D=25 A, R G=2.7 Ω
pF
ns
Gate Charge Characteristics 6)
V DD=15 V, I D=25 A,
V GS=0 to 5 V
nC
V
nC
Reverse Diode
Diode continous forward current
IS
Diode pulse current
I S,pulse
Diode forward voltage
V SD
V GS=0 V, I F=50 A,
T j=25 °C
-
0.92
1.2
V
Reverse recovery charge
Q rr
V R=15 V, I F=I S,
di F/dt =400 A/µs
-
-
10
nC
6)
Rev. 1.3
T C=25 °C
A
See figure 16 for gate charge parameter definition
page 3
2006-05-11
IPDH5N03LA G
1 Power dissipation
2 Drain current
P tot=f(T C)
I D=f(T C); V GS≥10 V
90
IPSH5N03LA G
60
80
50
70
60
40
I D [A]
P tot [W]
50
40
30
30
20
20
10
10
0
0
0
50
100
150
200
0
50
100
T C [°C]
150
200
T C [°C]
3 Safe operating area
4 Max. transient thermal impedance
I D=f(V DS); T C=25 °C; D =0
Z thJC=f(t p)
parameter: t p
parameter: D =t p/T
1000
10
1 µs
limited by on-state
resistance
10 µs
100
1
DC
1 ms
10
0.5
Z thJC [K/W]
I D [A]
100 µs
0.2
0.1
0.05
0.1
10 ms
0.02
0.01
single pulse
1
0.01
0.1
1
10
100
0
0
0
0
0
1
10-5
10-4
10-3
10-2
10-1
100
t p [s]
V DS [V]
Rev. 1.3
0
10-6
page 4
2006-05-11
IPDH5N03LA G
IPSH5N03LA G
5 Typ. output characteristics
6 Typ. drain-source on resistance
I D=f(V DS); T j=25 °C
R DS(on)=f(I D); T j=25 °C
parameter: V GS
parameter: V GS
100
20
4.5 V
10 V
3V
90
18
4.1 V
80
16
70
14
4.1 V
3.8 V
3.5 V
3.2 V
3.8 V
R DS(on) [mΩ]
I D [A]
60
50
3.5 V
40
30
12
10
4.5 V
8
6
3.2 V
20
10 V
4
3V
10
2
2.8 V
0
0
0
1
2
3
0
20
40
V DS [V]
60
80
100
I D [A]
7 Typ. transfer characteristics
8 Typ. forward transconductance
I D=f(V GS); |V DS|>2|I D|R DS(on)max
g fs=f(I D); T j=25 °C
parameter: T j
100
80
70
80
60
50
I D [A]
g fs [S]
60
40
40
30
20
20
175 °C
10
25 °C
0
0
0
1
2
3
4
5
Rev. 1.3
0
10
20
30
40
50
60
I D [A]
V GS [V]
page 5
2006-05-11
IPDH5N03LA G
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
R DS(on)=f(T j); I D=50 A; V GS=10 V
V GS(th)=f(T j); V GS=V DS
IPSH5N03LA G
parameter: I D
10
2.5
9
8
2
7
350 µA
98 %
5
1.5
V GS(th) [V]
R DS(on) [mΩ]
6
typ
4
35 µA
1
3
2
0.5
1
0
0
-60
-20
20
60
100
140
180
-60
-20
20
T j [°C]
60
100
140
180
T j [°C]
11 Typ. Capacitances
12 Forward characteristics of reverse diode
C =f(V DS); V GS=0 V; f =1 MHz
I F=f(V SD)
parameter: T j
104
1000
10000
25 °C
Ciss
Coss
1000
100
102
175 °C
Crss
0
25 °C, 98%
10
100
1
10
5
10
15
20
25
30
V DS [V]
Rev. 1.3
175 °C, 98%
I F [A]
C [pF]
103
0.0
0.5
1.0
1.5
2.0
V SD [V]
page 6
2006-05-11
IPDH5N03LA G
13 Avalanche characteristics
14 Typ. gate charge
I AS=f(t AV); R GS=25 Ω
V GS=f(Q gate); I D=25 A pulsed
parameter: Tj(start)
parameter: V DD
100
IPSH5N03LA G
12
15 V
10
100 °C
150 °C
5V
25 °C
20 V
V GS [V]
I AV [A]
8
10
6
4
2
1
0
1
10
100
1000
0
10
20
30
Q gate [nC]
t AV [µs]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V BR(DSS)=f(T j); I D=1 mA
29
V GS
28
Qg
27
V BR(DSS) [V]
26
25
24
V g s(th)
23
22
Q g(th)
21
Q sw
Q gs
20
-60
-20
20
60
100
140
Q g ate
Q gd
180
T j [°C]
Rev. 1.3
page 7
2006-05-11
IPDH5N03LA G
Package Outline
IPSH5N03LA G
PG-TO252-3-11
PG-TO252-3-11: Outline
Footprint:
Rev. 1.3
Packaging:
page 8
2006-05-11
IPDH5N03LA G
Package Outline
IPSH5N03LA G
PG-TO251-3-11
PG-TO251-3-11: Outline
PG-TO251-3-21: Outline
Rev. 1.3
page 9
2006-05-11
IPDH5N03LA G
IPSH5N03LA G
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com ).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Rev. 1.3
page 10
2006-05-11
Similar pages