PD - 96891A
AUTOMOTIVE MOSFET
IRF2804S-7P
HEXFET® Power MOSFET
Features
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
D
VDSS = 40V
G
RDS(on) = 1.6mΩ
S
Description
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely
efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
ID = 160A
S (Pin 2, 3 ,5,6,7)
G (Pin 1)
D
D
G
Absolute Maximum Ratings
S
S
S
S
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
320
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (See Fig. 9)
230
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
160
IDM
Pulsed Drain Current
1360
PD @TC = 25°C
Maximum Power Dissipation
330
W
VGS
Linear Derating Factor
Gate-to-Source Voltage
2.2
± 20
W/°C
V
EAS
Single Pulse Avalanche Energy (Thermally Limited)
630
mJ
c
EAS (tested)
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
c
h
d
1050
See Fig.12a,12b,15,16
g
S
A
mJ
-55 to + 175
°C
300 (1.6mm from case )
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
10 lbf•in (1.1N•m)
Thermal Resistance
Typ.
Max.
Units
–––
0.50
°C/W
RθCS
Case-to-Sink, Flat, Greased Surface
0.50
–––
RθJA
Junction-to-Ambient
–––
62
RθJA
Junction-to-Ambient (PCB Mount, steady state)
–––
40
RθJC
Junction-to-Case
j
Parameter
j
ij
HEXFET® is a registered trademark of International Rectifier.
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1
6/01/05
IRF2804S-7P
Static @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
Min. Typ. Max. Units
V
Conditions
Drain-to-Source Breakdown Voltage
40
–––
–––
VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.028
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on) SMD
Static Drain-to-Source On-Resistance
–––
1.2
1.6
mΩ
VGS = 10V, ID = 160A
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
VDS = VGS, ID = 250µA
gfs
Forward Transconductance
220
–––
–––
S
VDS = 10V, ID = 160A
IDSS
Drain-to-Source Leakage Current
µA
VDS = 40V, VGS = 0V
–––
–––
20
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
Qg
Total Gate Charge
–––
170
260
Qgs
Gate-to-Source Charge
–––
63
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
71
–––
td(on)
Turn-On Delay Time
–––
17
–––
tr
Rise Time
–––
150
–––
ID = 160A
td(off)
Turn-Off Delay Time
–––
110
–––
RG = 2.6Ω
tf
Fall Time
–––
105
–––
VGS = 10V
LD
Internal Drain Inductance
–––
4.5
–––
IGSS
LS
Internal Source Inductance
–––
7.5
e
VDS = 40V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
nC
ID = 160A
VDS = 32V
VGS = 10V
ns
nH
VDD = 20V
e
d
Between lead,
D
–––
6mm (0.25in.)
from package
and center of die contact
VGS = 0V
G
S
Ciss
Input Capacitance
–––
6930
–––
Coss
Output Capacitance
–––
1750
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
970
–––
ƒ = 1.0MHz, See Fig. 5
Coss
Output Capacitance
–––
5740
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
1570
–––
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
2340
–––
VGS = 0V, VDS = 0V to 32V
pF
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
320
ISM
(Body Diode)
Pulsed Source Current
–––
–––
1360
c
A
(Body Diode)
VSD
Diode Forward Voltage
–––
–––
1.3
V
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
–––
–––
43
48
65
72
ns
nC
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C,
L=0.049mH, RG = 25Ω, IAS = 160A, VGS =10V.
Part not recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to
80% VDSS.
2
Conditions
MOSFET symbol
D
showing the
integral reverse
G
p-n junction diode.
TJ = 25°C, IS = 160A, VGS = 0V
TJ = 25°C, IF = 160A, VDD = 20V
di/dt = 100A/µs
S
e
e
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
Rθ is measured at TJ of approximately 90°C.
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IRF2804S-7P
10000
10000
1000
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
100
4.5V
≤ 60µs PULSE WIDTH
Tj = 25°C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
BOTTOM
100
4.5V
≤ 60µs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
100
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
240
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current(Α)
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100.0
TJ = 175°C
10.0
TJ = 25°C
1.0
VDS = 15V
≤ 60µs PULSE WIDTH
TJ = 25°C
200
160
TJ = 175°C
120
80
40
VDS = 10V
380µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8.0
0
0
20
40
60
80
100
120
140
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRF2804S-7P
14000
ID= 160A
VGS, Gate-to-Source Voltage (V)
12000
C, Capacitance (pF)
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
10000
8000
Ciss
6000
4000
Coss
Crss
2000
VDS= 20V
16
12
8
4
0
0
1
10
0
100
100
150
1000.0
10000
ID, Drain-to-Source Current (A)
TJ = 175°C
100.0
10.0
TJ = 25°C
1.0
0.8
1.2
1.6
300
1000
100µsec
100
10
1
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
DC
0.1
0.1
0.4
250
OPERATION IN THIS AREA
LIMITED BY R DS (on)
VGS = 0V
0.0
200
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
ISD , Reverse Drain Current (A)
50
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
2.0
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS = 32V
2.4
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF2804S-7P
350
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
LIMITED BY PACKAGE
ID , Drain Current (A)
300
250
200
150
100
50
0
25
50
75
100
125
150
ID = 160A
VGS = 10V
1.5
1.0
0.5
175
-60 -40 -20
TC , Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
1
Thermal Response ( Z thJC )
D = 0.50
0.1
0.20
0.10
0.05
0.01
τJ
0.02
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τC
τ
τ2
Ri (°C/W) τi (sec)
0.1951 0.000743
0.3050
0.008219
Ci= τi/Ri
Ci i/Ri
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF2804S-7P
D.U.T
RG
VGS
20V
DRIVER
L
VDS
+
V
- DD
IAS
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS, Single Pulse Avalanche Energy (mJ)
2500
15V
ID
21A
33A
BOTTOM 160A
TOP
2000
1500
1000
500
0
tp
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
4.5
VGS(th) Gate threshold Voltage (V)
VG
Charge
Fig 13a. Basic Gate Charge Waveform
L
DUT
0
1K
Fig 13b. Gate Charge Test Circuit
6
VCC
4.0
3.5
3.0
ID = 1.0A
ID = 1.0mA
2.5
ID = 250µA
2.0
1.5
1.0
0.5
-75
-50 -25
0
25
50
75
100 125 150 175
TJ , Temperature ( °C )
Fig 14. Threshold Voltage vs. Temperature
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IRF2804S-7P
10000
Duty Cycle = Single Pulse
Avalanche Current (A)
1000
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
100
0.05
0.10
10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
800
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 160A
600
400
200
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
175
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF2804S-7P
D.U.T
Driver Gate Drive
+
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
D=
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
VDS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF2804S-7P
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
D2Pak - 7 Pin Part Marking Information
25
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9
IRF2804S-7P
D2Pak - 7 Pin Tape and Reel
IRF2804STRL-7P
IRF2804STRL-7P
IRF2804STRL-7P
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101]market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/05
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/