Vishay IRFBE30STRLPBF Power mosfet Datasheet

IRFBE30S, IRFBE30L, SiHFBE30S, SiHFBE30L
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Dynamic dV/dt Rating
800
RDS(on) (Ω)
VGS = 10 V
Qg (Max.) (nC)
78
• Fast Switching
Qgs (nC)
9.6
• Ease of Paralleling
Qgd (nC)
45
Configuration
D2PAK
(TO-263)
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
G
G
D
G
COMPLIANT
• Lead (Pb)-free Available
D
S
RoHS*
• Simple Drive Requirements
Single
I2PAK
(TO-262)
Available
• Repetitive Avalanche Rated
3.0
D
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
D2PAK (TO-263)
D2PAK (TO-263)
I2PAK (TO-262)
IRFBE30SPbF
IRFBE30STRLPbFa
IRFBE30LPbF
SiHFBE30S-E3
SiHFBE30STL-E3a
SiHFBE30L-E3
IRFBE30S
-
-
SiHFBE30S
-
-
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
800
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
UNIT
V
4.1
2.6
A
IDM
16
1.0
W/°C
Single Pulse Avalanche Energyb
EAS
260
mJ
Avalanche Currenta
IAR
4.1
A
Repetitive Avalanche Energya
EAR
13
mJ
Linear Derating Factor
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
for 10 s
6-32 or M3 screw
PD
125
W
dV/dt
2.0
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
10
lbf · in
1.1
N·m
Notes
a.
b.
c.
d.
Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
VDD = 50 V, starting TJ = 25 °C, L = 29 mH, RG = 25 Ω, IAS = 4.1 A (see fig. 12).
ISD ≤ 4.1 A, dI/dt ≤ 100 A/µs, VDD ≤ 600 V, TJ ≤ 150 °C.
1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91119
S-81432-Rev. A, 07-Jul-08
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IRFBE30S, IRFBE30L, SiHFBE30S, SiHFBE30L
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
-
62
Case-to-Sink, Flat, Greased Surface
RthCS
-
0.50
-
Maximum Junction-to-Case (Drain)
RthJC
-
-
1.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
800
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.90
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 800 V, VGS = 0 V
-
-
100
VDS = 640 V, VGS = 0 V, TJ = 125 °C
-
-
500
-
-
3.0
Ω
VDS = 100 V, ID = 2.5 A
2.5
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
1300
-
-
310
-
-
190
-
-
-
78
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 2.5 Ab
VGS = 10 V
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
pF
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
9.6
Gate-Drain Charge
Qgd
-
-
45
Turn-On Delay Time
td(on)
-
12
-
tr
-
33
-
-
82
-
-
30
-
-
4.5
-
-
7.5
-
-
-
4.1
-
-
16
-
-
1.8
-
480
720
ns
-
1.8
2.7
nC
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V
ID = 4.1 A, VDS = 400 V,
see fig. 6 and 13b
VDD = 400 V, ID = 4.1 A,
RG = 12 Ω, RD = 95 Ω, see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 4.1 A, VGS = 0 Vb
TJ = 25 °C, IF = 4.1 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 91119
S-81432-Rev. A, 07-Jul-08
IRFBE30S, IRFBE30L, SiHFBE30S, SiHFBE30L
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91119
S-81432-Rev. A, 07-Jul-08
www.vishay.com
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IRFBE30S, IRFBE30L, SiHFBE30S, SiHFBE30L
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91119
S-81432-Rev. A, 07-Jul-08
IRFBE30S, IRFBE30L, SiHFBE30S, SiHFBE30L
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
RG
+
-
I AS
V DD
VDS
10 V
tp
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91119
S-81432-Rev. A, 07-Jul-08
IAS
Fig. 12b - Unclamped Inductive Waveforms
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IRFBE30S, IRFBE30L, SiHFBE30S, SiHFBE30L
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91119
S-81432-Rev. A, 07-Jul-08
IRFBE30S, IRFBE30L, SiHFBE30S, SiHFBE30L
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
+
RG
+
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
Driver gate drive
P.W.
Period
D=
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level and 3 V drive devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91119.
Document Number: 91119
S-81432-Rev. A, 07-Jul-08
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
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Document Number: 91000
Revision: 18-Jul-08
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