Vishay IRFL9110TR Power mosfet Datasheet

IRFL9110, SiHFL9110
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
- 100
RDS(on) (Ω)
VGS = - 10 V
1.2
Qg (Max.) (nC)
8.7
Qgs (nC)
2.2
Qgd (nC)
4.1
Configuration
Single
Surface Mount
Available in Tape and Reel
Dynamic dV/dt Rating
Repetitive Avalanche Rated
P-Channel
Fast Switching
Ease of Paralleling
Lead (Pb)-free Available
Available
RoHS*
COMPLIANT
DESCRIPTION
S
SOT-223
•
•
•
•
•
•
•
•
G
D
P-Channel MOSFET
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The SOT-223 package is designed for surface-mount using
vapor phase, infrared, or wave soldering techniques. Its
unique package design allows for easy automatic
pick-and-place as with other SOT or SOIC packages but has
the added advantage of improved thermal performance due
to an enlarged tab for heatsinking. Power dissipation of
greater than 1.25 W is possible in a typical surface mount
application.
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
SOT-223
SOT-223
IRFL9110PbF
IRFL9110TRPbFa
SiHFL9110-E3
SiHFL210T-E3a
IRFL9110
IRFL9110TRa
SiHFL9110
SiHFL9110Ta
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Currenta
SYMBOL
VDS
VGS
VGS at - 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
Pulsed Drain
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
EAS
Single Pulse Avalanche Energyb
IAR
Avalanche Currenta
EAR
Peak Diode Recovery dV/dtc
Maximum Power Dissipation
TC = 25 °C
PD
TA = 25 °C
Maximum Power Dissipation (PCB Mount)e
dV/dt
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
TJ, Tstg
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 25 V, starting TJ = 25 °C, L = 7.7 mH, RG = 25 Ω, IAS = - 4.4 A (see fig. 12).
c. ISD ≤ - 4.4 A, dI/dt ≤ - 75 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91196
S-81369-Rev. A, 07-Jul-08
LIMIT
- 100
± 20
- 1.1
- 0.69
- 8.8
0.025
0.017
100
- 1.1
0.31
3.1
2.0
- 5.5
- 55 to + 150
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
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IRFL9110, SiHFL9110
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mount)a
PARAMETER
RthJA
-
-
60
Maximum Junction-to-Case (Drain)
RthJC
-
-
40
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = - 250 µA
- 100
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.091
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 µA
- 2.0
-
- 4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = - 100 V, VGS = 0 V
-
-
- 100
VDS = - 80 V, VGS = 0 V, TJ = 125 °C
-
-
- 500
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = - 0.66 Ab
VGS = - 10 V
VDS = - 50 V, ID = - 0.66 A
µA
-
-
1.2
Ω
0.82
-
-
S
-
200
-
-
94
-
-
18
-
-
-
8.7
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
2.2
Gate-Drain Charge
Qgd
-
-
4.1
Turn-On Delay Time
td(on)
-
10
-
tr
-
27
-
-
15
-
-
17
-
-
4.0
-
-
6.0
-
-
-
- 1.1
-
-
- 8.8
-
-
- 5.5
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
td(off)
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
VGS = - 10 V
ID = - 4.0 A, VDS = - 80 V,
see fig. 6 and 13b
VDD = - 50 V, ID = - 4.0 A,
RG = 24 Ω, RD = 11 Ω, see fig. 10b
tf
LD
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = - 1.1 A, VGS = 0 Vb
TJ = 25 °C, IF = - 4.0 A, dI/dt = 100 A/µsb
V
-
80
160
ns
-
0.15
0.30
µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 91196
S-81369-Rev. A, 07-Jul-08
IRFL9110, SiHFL9110
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Document Number: 91196
S-81369-Rev. A, 07-Jul-08
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFL9110, SiHFL9110
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91196
S-81369-Rev. A, 07-Jul-08
IRFL9110, SiHFL9110
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+VDD
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
td(on)
tr
td(off) tf
VGS
10 %
90 %
VDS
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91196
S-81369-Rev. A, 07-Jul-08
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IRFL9110, SiHFL9110
Vishay Siliconix
L
Vary tp to obtain
required IAS
IAS
VDS
D.U.T.
RG
VDS
+ V DD
VDD
IAS
tp
- 10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
VDS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91196
S-81369-Rev. A, 07-Jul-08
IRFL9110, SiHFL9110
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
+
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
+
- VDD
Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
*
ISD
VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91196.
Document Number: 91196
S-81369-Rev. A, 07-Jul-08
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Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
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Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
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