Kersemi IRFR120TRRPBF Power mosfet Datasheet

IRFR120, IRFU120, SiHFR120, SiHFU120
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Dynamic dV/dt Rating
100
RDS(on) (Ω)
VGS = 10 V
Available
• Repetitive Avalanche Rated
0.27
16
• Surface Mount (IRFR120/SiHFR120)
Qgs (nC)
4.4
• Straight Lead (IRFU120/SiHFU120)
Qgd (nC)
7.7
• Available in Tape and Reel
Qg (Max.) (nC)
Configuration
Single
RoHS*
COMPLIANT
• Fast Switching
• Ease of Paralleling
D
• Lead (Pb)-free Available
DPAK
(TO-252)
IPAK
(TO-251)
DESCRIPTION
G
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
IRFR120PbF
IRFR120TRPbFa
IRFR120TRRPbFa
IRFR120TRLPbFa
IPAK (TO-251)
IRFU120PbF
SiHFR120-E3
SiHFR120T-E3a
SiHFR120TR-E3a
SiHFR120TL-E3a
SiHFU120-E3
IRFR120
IRFR120TRa
IRFR120TRRa
IRFR120TRLa
IRFU120
SiHFR120
SiHFR120Ta
SiHFR120TRa
SiHFR120TLa
SiHFU120
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
100
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
Pulsed Drain
VGS at 10 V
TC = 25 °C
TC = 100 °C
Currenta
ID
IDM
V
7.7
4.9
A
31
Linear Derating Factor
0.33
Linear Derating Factor (PCB Mount)e
0.020
Single Pulse Avalanche Energyb
UNIT
W/°C
EAS
210
Currenta
IAR
7.7
A
Repetitive Avalanche Energya
EAR
4.2
mJ
Repetitive Avalanche
Maximum Power Dissipation
TC = 25 °C
Maximum Power Dissipation (PCB Mount)e
TA = 25 °C
Peak Diode Recovery dV/dtc
PD
dV/dt
42
2.5
5.5
mJ
W
V/ns
* Pb containing terminations are not RoHS compliant, exemptions may apply
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IRFR120, IRFU120, SiHFR120, SiHFU120
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
SYMBOL
LIMIT
UNIT
TJ, Tstg
- 55 to + 150
°C
260d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 5.3 mH, RG = 25 Ω, IAS = 7.7 A (see fig. 12).
c. ISD ≤ 9.2 A, dI/dt ≤ 110 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
-
50
Maximum Junction-to-Case (Drain)
RthJC
-
-
3.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
100
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.13
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 100 V, VGS = 0 V
-
-
25
VDS = 80 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 4.6 Ab
VGS = 10 V
VDS = 50 V, ID = 4.6 A
µA
-
-
0.27
Ω
1.6
-
-
S
-
360
-
-
150
-
-
34
-
-
-
16
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
4.4
Gate-Drain Charge
Qgd
-
-
7.7
Turn-On Delay Time
td(on)
-
6.8
-
tr
-
27
-
-
18
-
-
17
-
-
4.5
-
-
7.5
-
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
ID = 9.2 A, VDS = 80 V,
see fig. 6 and 13b
VDD = 50 V, ID = 9.2 A,
RG = 18 Ω, RD = 5.2 Ω, see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
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VGS = 10 V
Between lead,
6 mm (0.25") from
package and center of
die contact
pF
nC
ns
D
nH
G
S
IRFR120, IRFU120, SiHFR120, SiHFU120
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
-
-
7.7
-
-
31
-
-
2.5
-
130
260
ns
-
0.65
1.3
µC
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 7.7 A, VGS = 0 Vb
TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFR120, IRFU120, SiHFR120, SiHFU120
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
IRFR120, IRFU120, SiHFR120, SiHFU120
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR120, IRFU120, SiHFR120, SiHFU120
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
RG
+
-
I AS
V DD
VDS
10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
IRFR120, IRFU120, SiHFR120, SiHFU120
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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