Vishay IRFR1N60APBF Power mosfet Datasheet

IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Requirement
600
RDS(on) (Max.) (Ω)
VGS = 10 V
7.0
Qg (Max.) (nC)
14
Qgs (nC)
2.7
Qgd (nC)
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Single
COMPLIANT
• Lead (Pb)-free Available
D
DPAK
(TO-252)
RoHS*
• Fully Characterized Capacitance and Avalanche Voltage
and Current
8.1
Configuration
Available
APPLICATIONS
IPAK
(TO-251)
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
G
• Power Factor Correction
S
TYPICAL SMPS TOPOLOGIES
N-Channel MOSFET
• Low Power Single Transistor Flyback
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
IPAK (TO-251)
IRFR1N60APbF
IRFR1N60ATRLPbFa
IRFR1N60ATRPbFa
IRFR1N60ATRRPbFa
IRFU1N60APbF
SiHFR1N60A-E3
SiHFR1N60ATL-E3a
SiHFR1N60AT-E3a
SiHFR1N60ATR-E3a
SiHFU1N60A-E3
IRFR1N60A
-
IRFR1N60ATRa
-
IRFU1N60A
SiHFR1N60A
-
SiHFR1N60ATa
-
SiHFU1N60A
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
600
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
Pulsed Drain
VGS at 10 V
TC = 25 °C
TC = 100 °C
Currenta
ID
IDM
Linear Derating Factor
Energyb
UNIT
V
1.4
0.89
A
5.6
0.28
W/°C
EAS
93
mJ
Repetitive Avalanche Currenta
IAR
1.4
A
Energya
EAR
3.6
mJ
Single Pulse Avalanche
Repetitive Avalanche
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
PD
36
W
dV/dt
3.8
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 95 mH, RG = 25 Ω, IAS = 1.4 A (see fig. 12).
c. ISD ≤ 1.4 A, dI/dt ≤ 180 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
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IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
50
Maximum Junction-to-Case (Drain)
RthJC
-
3.5
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
VDS
VGS = 0 V, ID = 250 µA
600
-
-
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
Zero Gate Voltage Drain Current
IDSS
VDS = 600 V, VGS = 0 V
-
-
25
VDS = 480 V, VGS = 0 V, TJ = 150 °C
-
-
250
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 0.84 Ab
VGS = 10 V
VDS = 50 V, ID = 0.84 A
V
nA
µA
-
-
7.0
Ω
0.88
-
-
S
-
229
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 0 V
Coss eff.
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
32.6
-
-
2.4
-
VDS = 1.0 V, f = 1.0 MHz
-
320
-
VDS = 480 V, f = 1.0 MHz
-
11.5
-
-
130
-
VDS = 0 V to 480
VGS = 10 V
Vc
ID = 1.4 A, VDS = 400 V,
see fig. 6 and 13b
-
-
14
-
-
2.7
pF
nC
Gate-Drain Charge
Qgd
-
-
8.1
Turn-On Delay Time
td(on)
-
9.8
-
-
14
-
-
18
-
-
20
-
-
-
1.4
-
-
5.6
-
-
1.6
-
290
440
ns
-
510
760
µC
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = 250 V, ID = 1.4 A,
RG = 2.15 Ω, RD = 178 Ω, see fig. 10b
tf
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 1.4 A, VGS = 0 Vb
TJ = 25 °C, IF = 1.4 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91267
S-81367-Rev. A, 21-Jul-08
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
1
0.1
4.5V
20μs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
100
TJ = 150 ° C
1
TJ = 25 ° C
0.1
4.0
Fig. 1 - Typical Output Characteristics
I D , Drain-to-Source Current (A)
1
4.5V
20μs PULSE WIDTH
TJ = 150 ° C
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1
6.0
7.0
8.0
9.0
Fig. 3 - Typical Transfer Characteristics
TOP
0.1
5.0
VGS , Gate-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
10
V DS = 100V
20μs PULSE WIDTH
ID = 1.4A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
10
V GS = 0V,
f = 1MHz
C iss = C gs + C gd, C dsSHORTED
C rss = C gd
C oss = C ds + C gd
ISD , Reverse Drain Current (A)
C, Capacitance (pF)
10000
1000
C iss
100
C oss
10
TJ = 150 ° C
1
TJ = 25 ° C
Crss
1
0.1
0.4
A
1
10
100
1000
1.0
1.2
100
ID = 1.4A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS = 480V
VDS = 300V
VDS = 120V
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
0.8
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
16
0.6
VSD ,Source-to-Drain Voltage (V)
V DS , Drain-to-Source Voltage (V)
20
V GS = 0 V
12
8
10
10us
100us
1
1ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
2
4
6
8
10
12
14
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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0.1
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
10ms
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
RD
VDS
1.6
VGS
D.U.T.
ID , Drain Current (A)
RG
+
- VDD
1.2
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
0.8
Fig. 10a - Switching Time Test Circuit
VDS
0.4
90 %
0.0
25
50
75
100
125
150
10 %
VGS
TC , Case Temperature ( ° C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
PDM
0.02
0.01
0.1
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
Fig. 12b - Unclamped Inductive Waveforms
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IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
200
ID
0.65A
0.9A
BOTTOM 1.4A
770
TOP
160
120
80
40
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
V DSav , Avalanche Voltage (V)
EAS , Single Pulse Avalanche Energy (mJ)
Vishay Siliconix
750
730
710
690
670
0.0
A
0.4
0.8
1.2
1.6
I av , Avalanche Current (A)
Fig. 12d - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91267.
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
www.vishay.com
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Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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Document Number: 91000
Revision: 18-Jul-08
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