IRFR210, IRFU210, SiHFR210, SiHFU210 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 200 RDS(on) (Ω) VGS = 10 V 1.5 • Repetitive Avalanche Rated • Surface Mount (IRFR210/SiHFR210) Qg (Max.) (nC) 8.2 Qgs (nC) 1.8 • Straight Lead (IRFU210/SiHFU210) 4.5 • Available in Tape and Reel Qgd (nC) Configuration Available RoHS* COMPLIANT • Fast Switching Single • Ease of Paralleling D • Lead (Pb)-free Available DPAK (TO-252) IPAK (TO-251) DESCRIPTION G S N-Channel MOSFET Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) IRFR210PbF SiHFR210-E3 IRFR210 SiHFR210 DPAK (TO-252) IRFR210TRLPbFa SiHFR210TL-E3a IRFR210TRLa SiHFR210TLa DPAK (TO-252) IRFR210TRPbFa SiHFR210T-E3a IRFR210TRa SiHFR210Ta DPAK (TO-252) IRFR210TRRa SiHFR210TRa IPAK (TO-251) IRFU210PbF SiHFU210-E3 IRFU210 SiHFU210 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Currenta SYMBOL VDS VGS VGS at 10 V TC = 25 °C TC = 100 °C ID Pulsed Drain IDM Linear Derating Factor Linear Derating Factor (PCB Mount)e EAS Single Pulse Avalanche Energyb Avalanche Currenta IAR EAR Repetitive Avalanche Energya Maximum Power Dissipation TC = 25 °C PD TA = 25 °C Maximum Power Dissipation (PCB Mount)e Peak Diode Recovery dV/dtc dV/dt Operating Junction and Storage Temperature Range TJ, Tstg Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 28 mH, RG = 25 Ω, IAS = 2.6 A (see fig. 12). c. ISD ≤ 2.6 A, dI/dt ≤ 70 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). LIMIT 200 ± 20 2.6 1.7 10 0.20 0.020 130 2.7 2.5 25 2.5 5.0 - 55 to + 150 260d UNIT V A W/°C mJ A mJ W V/ns °C www.kersemi.com 1 IRFR210, IRFU210, SiHFR210, SiHFU210 THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 5.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 µA 200 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.30 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 200 V, VGS = 0 V - - 25 VDS = 160 V, VGS = 0 V, TJ = 125 °C - - 250 - - 1.5 Ω 0.80 - - S - 140 - - 53 - - 15 - Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 1.6 Ab VGS = 10 V VDS = 50 V, ID = 1.6 Ab µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - - 8.2 - - 1.8 Qgd - - 4.5 td(on) - 8.2 - tr - 17 - - 14 - - 8.9 - - 4.5 - - 7.5 - - - 2.6 - - 10 td(off) VGS = 10 V ID = 3.3 A, VDS = 160 V, see fig. 6 and 13b VDD = 100 V, ID = 3.3 A, RG = 24 Ω, RD = 30 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact D pF nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode A G S TJ = 25 °C, IS = 2.6 A, VGS = 0 Vb TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/µsb - - 2.0 V - 150 310 ns - 0.60 1.4 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.kersemi.com 2 D IRFR210, IRFU210, SiHFR210, SiHFU210 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR210, IRFU210, SiHFR210, SiHFU210 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.kersemi.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area IRFR210, IRFU210, SiHFR210, SiHFU210 VDS VGS RD D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case www.kersemi.com 5 IRFR210, IRFU210, SiHFR210, SiHFU210 L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T RG + - I AS V DD VDS 10 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kersemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR210, IRFU210, SiHFR210, SiHFU210 Peak Diode Recovery dV/dt Test Circuit + D.U.T Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel www.kersemi.com 7