Vishay IRFZ48LPBF Power mosfet Datasheet

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Qg (Max.) (nC)
Qgs (nC)
Qgd (nC)
Configuration
• Halogen-free According to IEC 61249-2-21
Definition
• Advanced Process Technology
• Surface Mount (IRFZ48S, SiHFZ48S)
• Low-Profile Through-Hole (IRFZ48L, SiHFZ48L)
• 175 °C Operating Temperature
• Fast Switching
• Compliant to RoHS Directive 2002/95/EC
60
VGS = 10 V
0.018
110
29
36
Single
DESCRIPTION
D
G
G
Third generation Power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The D2PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2 W in a typical surface mount application.
The through-hole version (IRFZ48L, SiHFZ48L) is available
for low-profile applications.
D2PAK (TO-263)
I2PAK (TO-262)
D
S
G
D
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
SiHFZ48S-GE3
IRFZ48SPbF
SiHFZ48S-E3
I2PAK (TO-262)
IRFZ48LPbF
SiHFZ48L-E3
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Currentf
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
Currenta, e
IDM
Pulsed Drain
Linear Derating Factor
Single Pulse Avalanche Energyb, e
Maximum Power Dissipation
ID
EAS
TC = 25 °C
TA = 25 °C
PD
dV/dt
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
TJ, Tstg
for 10 s
Soldering Recommendations (Peak Temperature)d
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, Starting TJ = 25 °C, L = 22 μH, Rg = 25 , IAS = 72 A (see fig. 12).
c. ISD  72 A, dI/dt  200 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. Uses IRFZ48, SiHFZ48 data and test conditions.
f. Calculated continuous current based on maximum allowable junction temperature.
LIMIT
60
± 20
50
50
290
1.3
100
190
3.7
4.5
- 55 to + 175
300
UNIT
V
A
W/°C
mJ
W
V/ns
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 90377
S11-1045-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mount)a
PARAMETER
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
0.8
UNIT
°C / W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VDS
VGS = 0, ID = 250 μA
60
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mAc
-
0.060
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 60 V, VGS = 0 V
-
-
25
VDS = 48 V, VGS = 0 V, TJ = 150 °C
-
-
250
-
-
0.018

27
-
-
S
-
2400
-
-
1300
-
-
190
-
-
-
110
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 43 Ab
VGS = 10 V
VDS = 25 V, ID = 43
Ab
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5c
pF
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
29
Gate-Drain Charge
Qgd
-
-
36
Turn-On Delay Time
td(on)
-
8.1
-
-
250
-
-
210
-
-
250
-
-
7.5
-
-
-
50c
-
-
290
-
-
2.0
-
120
180
ns
-
500
800
μC
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Internal Source Inductance
LS
VGS = 10 V
ID = 72 A, VDS = 48 V,
see fig. 6 and 13b, c
VDD = 30 V, ID = 72 A,
Rg = 9.1 , RD = 0.34 , see fig. 10b, c
Between lead, and center of die contact
nC
ns
nH
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 72 A, VGS = 0 Vb
TJ = 25 °C, IF = 72 A, dI/dt = 100 A/μsb, c
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. Uses IRFZ48/SiHFZ48 data and test conditions.
d. Calculated continuous current based on maximum allowable junction temperature.
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Document Number: 90377
S11-1045-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Document Number: 90377
S11-1045-Rev. C, 30-May-11
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 90377
S11-1045-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
RD
VDS
VGS
D.U.T.
Rg
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 90377
S11-1045-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
Rg
+
-
I AS
V DD
VDS
10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
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Fig. 13b - Gate Charge Test Circuit
Document Number: 90377
S11-1045-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90377.
Document Number: 90377
S11-1045-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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Document Number: 91000
Revision: 11-Mar-11
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