IRF IRHLNA77064 Radiation hardened logic level power mosfet surface mount (smd-2) Datasheet

PD-97177A
RADIATION HARDENED
LOGIC LEVEL POWER MOSFET
SURFACE MOUNT (SMD-2)
IRHLNA77064
60V, N-CHANNEL
TECHNOLOGY
™
Product Summary
Part Number
IRHLNA77064
Radiation Level
100K Rads (Si)
RDS(on)
0.012Ω
ID
56A*
IRHLNA73064
300K Rads (Si)
0.012Ω
56A*
SMD-2
International Rectifier’s R7 TM Logic Level Power
MOSFETs provide simple solution to interfacing CMOS
and TTL control circuits to power devices in space and
other radiation environments. The threshold voltage
remains within acceptable operating limits over the
full operating temperature and post radiation. This is
achieved while maintaining single event gate rupture
and single event burnout immunity.
These devices are used in applications such as current
boost low signal source in PWM, voltage comparator
and operational amplifiers.
Features:
n
n
n
n
n
n
n
n
n
n
5V CMOS and TTL Compatible
Fast Switching
Single Event Effect (SEE) Hardened
Low Total Gate Charge
Simple Drive Requirements
Ease of Paralleling
Hermetically Sealed
Ceramic Package
Surface Mount
Light Weight
Absolute Maximum Ratings
Pre-Irradiation
Parameter
ID @VGS = 4.5V,TC = 25°C
ID @VGS = 4.5V,TC = 100°C
IDM
PD @ TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
T STG
Continuous Drain Current
Continuous Drain Current
Pulsed Drain Current À
Max. Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy Á
Avalanche Current À
Repetitive Avalanche Energy À
Peak Diode Recovery dv/dt Â
Operating Junction
Storage Temperature Range
Pckg. Mounting Surface Temp.
Weight
Units
56*
56*
224
250
2.0
±10
402
56
25
6.9
-55 to 150
300 (for 5s)
3.3 (Typical)
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
g
* Current is limited by package
For footnotes refer to the last page
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1
04/06/07
IRHLNA77064
Pre-Irradiation
Electrical Characteristics @ Tj = 25°C (Unless Otherwise Specified)
Parameter
BVDSS
Min
Drain-to-Source Breakdown Voltage
∆BV DSS /∆T J Temperature Coefficient of Breakdown
Voltage
RDS(on)
Static Drain-to-Source On-State
Resistance
VGS(th)
Gate Threshold Voltage
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient
gfs
Forward Transconductance
IDSS
Zero Gate Voltage Drain Current
Typ Max Units
Test Conditions
60
—
—
V
VGS = 0V, ID = 250µA
—
0.07
—
V/°C
Reference to 25°C, ID = 1.0mA
—
—
0.012
Ω
1.0
—
32
—
—
—
-6.6
—
—
—
2.0
—
—
1.0
10
V
mV/°C
S
nA
IGSS
IGSS
Qg
Q gs
Q gd
td(on)
tr
td(off)
tf
LS + LD
Gate-to-Source Leakage Forward
Gate-to-Source Leakage Reverse
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain (‘Miller’) Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Inductance
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.0
100
-100
151
30
70
51
170
110
17
—
Ciss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
—
—
—
10220
2343
40
—
—
—
Rg
Gate Resistance
VGS = 4.5V, ID = 56A
Ã
nC
V DS = 10V, IDS = 56A Ã
VDS= 48V ,VGS=0V
VDS = 48V,
VGS = 0V, TJ = 125°C
VGS = 10V
VGS = -10V
VGS = 4.5V, ID = 56A
VDS = 30V
ns
VDD = 30V, ID = 56A,
VGS = 4.5V, RG = 2.35Ω
µA
nH
pF
Ω
0.56
VDS = VGS, ID = 250µA
Measured from the center of
drain pad to center of source pad
VGS = 0V, VDS = 25V
f = 100KHz
f = 1.0MHz, open drain
Source-Drain Diode Ratings and Characteristics
Parameter
IS
ISM
VSD
t rr
Q RR
Min Typ Max Units
Continuous Source Current (Body Diode)
Pulse Source Current (Body Diode) À
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
ton
Forward Turn-On Time
* Current is limited by package
—
—
—
—
—
—
—
—
—
—
56*
224
1.2
214
1.16
Test Conditions
A
V
ns
µC
Tj = 25°C, IS = 56A, VGS = 0V Ã
Tj = 25°C, IF =56A, di/dt ≤ 100A/µs
VDD ≤ 30V Ã
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance
Parameter
RthJC
RthJ-PCB
Junction-to-Case
Junction-to-PC board
Min Typ Max Units
—
—
—
1.6
0.5
—
°C/W
Test Conditions
soldered to a 2” square copper-cladboard
Note: Corresponding Spice and Saber models are available on International Rectifier Web site.
For footnotes refer to the last page
2
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Radiation Characteristics
Pre-Irradiation
IRHLNA77064
International Rectifier Radiation Hardened MOSFETs are tested to verify their radiation hardness capability.
The hardness assurance program at International Rectifier is comprised of two radiation environments.
Every manufacturing lot is tested for total ionizing dose (per notes 5 and 6) using the TO-3 package. Both
pre- and post-irradiation performance are tested and specified using the same drive circuitry and test
conditions in order to provide a direct comparison.
Table 1. Electrical Characteristics @ Tj = 25°C, Post Total Dose Irradiation ÄÅ
Parameter
BVDSS
V GS(th)
IGSS
IGSS
IDSS
RDS(on)
RDS(on)
VSD
Units
Test Conditions ˆ
V
µA
VGS = 0V, ID = 250µA
VGS = VDS , ID = 250µA
VGS = 10V
VGS = -10V
VDS = 48V, VGS=0V
0.01
Ω
VGS = 4.5V, ID = 56A
—
0.012
Ω
VGS = 4.5V, ID = 56A
—
1.2
V
V GS = 0V, ID = 56A
Upto 300K Rads (Si)1
Min
Max
Drain-to-Source Breakdown Voltage
Gate Threshold Voltage
Gate-to-Source Leakage Forward
Gate-to-Source Leakage Reverse
Zero Gate Voltage Drain Current
Static Drain-to-Source „
On-State Resistance (TO-3)
Static Drain-to-Source On-state „
Resistance (SMD-2)
60
1.0
—
—
—
—
2.0
100
-100
10
—
Diode Forward Voltage„
nA
1. Part numbers IRHLNA77064, IRHLNA73064
International Rectifier radiation hardened MOSFETs have been characterized in heavy ion environment for
Single Event Effects (SEE). Single Event Effects characterization is illustrated in Fig. a and Table 2.
Table 2. Single Event Effect Safe Operating Area
Ion
LET
Energy Range
2
VDS (V)
@VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS=
(MeV/(mg/cm ))
(MeV)
(µm)
0V
-3V
-4V
-5V
-6V
-7V
-8V
-9V
-10V
Br
I
37
60
305
370
39
34
60
60
60
60
50
60
45
60
40
30
30
20
25
10
20
10
15
-
Au
84
390
30
60
60
60
50
25
-
-
-
80
VDS
60
Br
40
I
20
Au
0
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10
VGS
Fig a. Single Event Effect, Safe Operating Area
For footnotes refer to the last page
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3
IRHLNA77064
Pre-Irradiation
1000
VGS
TOP
10V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
BOTTOM 2.5V
100
2.5V
10
60µs PULSE WIDTH
Tj = 25°C
1
100
2.5V
10
60µs PULSE WIDTH
Tj = 150°C
1
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
T J = 150°C
100
T J = 25°C
VDS = 25V
15
60µs PULSE
WIDTH
10
ID = 56A
1.6
1.2
0.8
0.4
VGS = 4.5V
0.0
2.5
3
3.5
4
4.5
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
4
VGS
10V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
BOTTOM 2.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
5
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
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IRHLNA77064
30
ID = 56A
25
20
15
T J = 150°C
10
5
T J = 25°C
0
2
3
4
5
6
7
8
9
RDS(on), Drain-to -Source On Resistance ( mΩ)
RDS(on), Drain-to -Source On Resistance (m Ω)
Pre-Irradiation
13
T J = 150°C
12
11
10
9
TJ = 25°C
8
7
Vgs = 4.5V
6
10 11 12
0
20
60
80
100
ID, Drain Current (A)
VGS, Gate -to -Source Voltage (V)
Fig 5. Typical On-Resistance Vs
Gate Voltage
Fig 6. Typical On-Resistance Vs
Drain Current
85
2.5
ID = 1.0mA
VGS(th) Gate threshold Voltage (V)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
40
75
2.0
1.5
1.0
0.5
ID = 50µA
ID = 250µA
ID = 1.0mA
ID = 150mA
0.0
65
-60 -40 -20
0
20
40
60
80 100 120 140 160
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Temperature ( °C )
T J , Temperature ( °C )
Fig 7. Typical Drain-to-Source
Breakdown Voltage Vs Temperature
Fig 8. Typical Threshold Voltage Vs
Temperature
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5
IRHLNA77064
20000
12
VGS = 0V,
f = 100 KHz
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
16000
ID = 56A
VGS, Gate-to-Source Voltage (V)
18000
C, Capacitance (pF)
Pre-Irradiation
C oss = C ds + C gd
14000
12000
Ciss
10000
Coss
8000
6000
4000
Crss
2000
10
VDS = 48V
VDS = 30V
VDS = 12V
8
6
4
2
FOR TEST CIRCUIT
SEE FIGURE 16
0
0
1
10
100
0
30 60 90 120 150 180 210 240 270 300
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 10. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 9. Typical Capacitance Vs.
Drain-to-Source Voltage
120
1000
100
100
ID , Drain Current (A)
ISD, Reverse Drain Current (A)
LIMITED BY PACKAGE
T J = 150°C
10
T J = 25°C
1
80
60
40
20
VGS = 0V
0.1
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD , Source-to-Drain Voltage (V)
Fig 11. Typical Source-to-Drain Diode
Forward Voltage
6
1.6
25
50
75
100
125
150
TC , Case Temperature (°C)
Fig 12. Maximum Drain Current Vs.
Case Temperature
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Pre-Irradiation
IRHLNA77064
Thermal Response ( Z thJC )
1
D = 0.50
P DM
0.20
0.1
t1
0.10
0.05
t2
SINGLE PULSE
( THERMAL RESPONSE )
0.02
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.01
1E-005
0.0001
0.001
0.01
0.1
1
t 1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
800
EAS , Single Pulse Avalanche Energy (mJ)
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µs
100
1ms
10ms
10
Tc = 25°C
Tj = 150°C
Single Pulse
10
VDS , Drain-to-Source Voltage (V)
Fig 14. Maximum Safe Operating Area
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TOP
600
500
400
300
200
100
0
1
1
ID
25A
35.4A
BOTTOM
56A
700
100
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 15a. Maximum Avalanche Energy
Vs. Drain Current
7
IRHLNA77064
Pre-Irradiation
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T.
RG
+
- VDD
IAS
VGS
20V
A
0.01Ω
tp
Fig 15b. Unclamped Inductive Test Circuit
I AS
Fig 15c. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
4.5V
50KΩ
.2µF
12V
QGS
.3µF
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
IG
Charge
Fig 16a. Basic Gate Charge Waveform
VDS
Fig 16b. Gate Charge Test Circuit
RD
VDS
90%
VGS
D.U.T.
RG
ID
Current Sampling Resistors
VDD
+
-
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 17a. Switching Time Test Circuit
8
10%
VGS
td(on)
tr
t d(off)
tf
Fig 17b. Switching Time Waveforms
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Pre-Irradiation
IRHLNA77064
Footnotes:
À Repetitive Rating; Pulse width limited by
maximum junction temperature.
Á VDD = 25V, starting TJ = 25°C, L= 0.26mH
Peak IL = 56A, VGS = 10V
 ISD ≤ 56A, di/dt ≤ 350A/µs,
VDD ≤ 60V, TJ ≤ 150°C
à Pulse width ≤ 300 µs; Duty Cycle ≤ 2%
Ä Total Dose Irradiation with VGS Bias.
10 volt VGS applied and V DS = 0 during
irradiation per MIL-STD-750, method 1019, condition A.
Å Total Dose Irradiation with VDS Bias.
48 volt VDS applied and V GS = 0 during
irradiation per MlL-STD-750, method 1019, condition A.
Case Outline and Dimensions — SMD-2
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 04/2007
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9