IRLR2908
IRLU2908
I-Pak
IRLU2908
D-Pak
IRLR2908
Features
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
l
l
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Description
The D-Pak is designed for surface mounting
using vapor phase, infrared, or wavesolde
ring techniques. The straight lead version
(IRFU series) is for through-hole mounting
applications. Power dissipation levels up to
1.5 watts are possible in typical surface mount
applications.
D
VDSS = 80V
RDS(on) = 28mΩ
G
ID = 30A
S
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
39
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (See Fig. 9)
28
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
30
IDM
Pulsed Drain Current
150
PD @TC = 25°C
Maximum Power Dissipation
120
W
VGS
Linear Derating Factor
Gate-to-Source Voltage
0.77
± 16
W/°C
V
180
mJ
EAS
c
EAS (tested)
Single Pulse Avalanche Energy (Thermally Limited)
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
EAR
dv/dt
TJ
TSTG
i
c
d
250
See Fig.12a,12b,15,16
h
Peak Diode Recovery dv/dt e
Repetitive Avalanche Energy
A
mJ
2.3
-55 to + 175
Operating Junction and
V/ns
°C
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
2014-8-25
j
1
Typ.
Max.
Units
–––
1.3
°C/W
–––
40
–––
110
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IRLR2908/IRLU2908
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
80
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.085
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
22.5
28
mΩ
–––
25
30
V
VGS = 0V, ID = 250µA
VGS = 10V, ID = 23A
VGS = 4.5V, ID = 20A
VGS(th)
Gate Threshold Voltage
1.0
–––
2.5
V
gfs
IDSS
Forward Transconductance
35
–––
–––
S
VDS = 25V, ID = 23A
Drain-to-Source Leakage Current
–––
–––
20
µA
VDS = 80V, VGS = 0V
–––
–––
250
IGSS
Gate-to-Source Forward Leakage
–––
–––
200
nA
VGS = 16V
nC
ID = 23A
f
f
VDS = VGS, ID = 250µA
VDS = 80V, VGS = 0V, TJ = 125°C
Gate-to-Source Reverse Leakage
–––
–––
-200
Qg
Total Gate Charge
–––
22
33
VGS = -16V
Qgs
Gate-to-Source Charge
–––
6.0
9.1
Qgd
Gate-to-Drain ("Miller") Charge
–––
11
17
td(on)
Turn-On Delay Time
–––
12
–––
tr
Rise Time
–––
95
–––
ID = 23A
td(off)
Turn-Off Delay Time
–––
36
–––
RG = 8.3Ω
tf
Fall Time
–––
55
–––
LD
Internal Drain Inductance
–––
4.5
–––
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
and center of die contact
VGS = 0V
VDS = 64V
VGS = 4.5V
ns
VDD = 40V
VGS = 4.5V
nH
f
Between lead,
D
G
S
Ciss
Input Capacitance
–––
1890
–––
Coss
Output Capacitance
–––
260
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
35
–––
ƒ = 1.0MHz, See Fig. 5
Coss
Output Capacitance
–––
1920
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
170
–––
VGS = 0V, VDS = 64V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
310
–––
VGS = 0V, VDS = 0V to 64V
pF
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
(Body Diode)
Diode Forward Voltage
–––
trr
Reverse Recovery Time
–––
Qrr
Reverse Recovery Charge
–––
ton
Forward Turn-On Time
2014-8-25
–––
–––
39
A
–––
c
Conditions
MOSFET symbol
D
150
showing the
integral reverse
–––
1.3
V
p-n junction diode.
TJ = 25°C, IS = 23A, VGS = 0V
75
110
ns
210
310
nC
–––
G
S
f
TJ = 25°C, IF = 23A, VDD = 25V
di/dt = 100A/µs
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRLR2908/IRLU2908
1000
1000
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
2.5V
1
0.1
100
BOTTOM
VGS
15V
10V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
2.5V
10
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.01
0.01
0.1
1
10
0.01
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
G FS , Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
60
100
T J = 175°C
T J = 25°C
10
VDS = 25V
20µs PULSE WIDTH
TJ = 25°C
50
40
T J = 175°C
30
20
10
VDS = 10V
20µs PULSE WIDTH
1
2
3
4
5
0
0
VGS , Gate-to-Source Voltage (V)
10
20
30
40
50
60
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
Fig 3. Typical Transfer Characteristics
2014-8-25
3
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IRLR2908/IRLU2908
100000
VGS , Gate-to-Source Voltage (V)
ID= 23A
Coss = Cds + Cgd
10000
C, Capacitance(pF)
5.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Ciss
1000
Coss
100
Crss
4.0
VDS= 16V
3.0
2.0
1.0
0.0
10
1
10
0
100
5
10
15
20
25
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000
100.00
ID, Drain-to-Source Current (A)
1000.00
ISD, Reverse Drain Current (A)
VDS= 64V
VDS= 40V
100
T J = 175°C
10.00
T J = 25°C
1.00
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
10
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
10
100
1000
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
2014-8-25
1
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
4
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IRLR2908/IRLU2908
40
35
ID, Drain Current (A)
30
25
20
15
10
5
ID = 38A
2.5
VGS = 4.5V
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
3.0
0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
175
-60 -40 -20 0
T C , Case Temperature (°C)
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
P DM
t1
0.01
SINGLE PULSE
( THERMAL RESPONSE )
t2
Notes:
1. Duty factor D =
2. Peak T
t1/ t 2
J = P DM x Z thJC
+T C
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
2014-8-25
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IRLR2908/IRLU2908
400
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
VGS
EAS , Single Pulse Avalanche Energy (mJ)
15V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
ID
9.3A
16A
BOTTOM 23A
TOP
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
2.5
VGS(th) Gate threshold Voltage (V)
QGS
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
2.0
1.5
ID = 250µA
1.0
0.5
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 14. Threshold Voltage vs. Temperature
Fig 13b. Gate Charge Test Circuit
2014-8-25
6
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IRLR2908/IRLU2908
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.01
10
0.05
0.10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
200
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 23A
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy
vs. Temperature
2014-8-25
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
7
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IRLR2908/IRLU2908
D.U.T
Driver Gate Drive
+
+
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
Period
P.W.
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
VDS
VGS
RD
D.U.T.
RG
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
2014-8-25
8
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IRLR2908/IRLU2908
TO-252AA (D-Pak) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.40 (.370)
1.02 (.040)
1.64 (.025)
1
2
LEAD ASSIGNMENTS
3
1 - GATE
-B-
1.52 (.060)
1.15 (.045)
3X
2X
1.14 (.045)
0.76 (.030)
0.89 (.035)
0.64 (.025)
0.25 (.010)
2 - DRAIN
0.51 (.020)
MIN.
3 - SOURCE
4 - DRAIN
0.58 (.023)
0.46 (.018)
M A M B
NOTES:
2.28 (.090)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4.57 (.180)
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
TO-252AA (D-Pak) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: THIS IS AN IRF R120
WITH ASSEMBLY
LOT CODE 9U1P
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
9U
016
1P
DATE CODE
YEAR = 0
WEEK = 16
AS SEMBLY
LOT CODE
Notes: T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 1999
IN THE ASS EMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
12
AS S EMBLY
LOT CODE
2014-8-25
PART NUMBER
9
916A
34
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
www.kersemi.com
IRLR2908/IRLU2908
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A-
0.58 (.023)
0.46 (.018)
1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
LEAD ASSIGNMENTS
4
1 - GATE
2 - DRAIN
6.45 (.245)
5.68 (.224)
1
2
3
-B2.28 (.090)
1.91 (.075)
3X
3 - SOURCE
4 - DRAIN
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1.14 (.045)
0.76 (.030)
2.28 (.090)
3X
9.65 (.380)
8.89 (.350)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
0.89 (.035)
0.64 (.025)
1.14 (.045)
0.89 (.035)
0.25 (.010)
M A M B
0.58 (.023)
0.46 (.018)
2X
I-Pak (TO-251AA) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WITH AS S EMBLY
LOT CODE 9U1P
INTERNATIONAL
RECT IFIER
LOGO
IRFU120
016
9U
1P
DATE CODE
YEAR = 0
WEEK = 16
AS SEMBLY
LOT CODE
Notes: T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WITH AS SEMBLY
LOT CODE 5678
AS S EMBLED ON WW 19, 1999
IN T HE ASS EMBLY LINE "A"
INT ERNATIONAL
RECT IFIER
LOGO
IRFU120
919A
56
ASS EMBLY
LOT CODE
2014-8-25
PART NUMBER
10
78
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
www.kersemi.com
IRLR2908/IRLU2908
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
Notes:
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.71mH, RG = 25Ω, IAS = 23A, VGS =10V. Part not recommended for use above
this value.
ISD ≤ 23A, di/dt ≤ 400A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This value determined from sample failure population. 100% tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer
to application note #AN-994.
2014-8-25
11
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