Vishay IRLZ14SPBF Power mosfet Datasheet

IRLZ14S, IRLZ14L, SiHLZ14S, SiHLZ14L
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
•
•
•
•
•
•
60
RDS(on) (Ω)
VGS = 5 V
0.20
Qg (Max.) (nC)
8.4
Qgs (nC)
3.5
Qgd (nC)
6.0
Configuration
Single
COMPLIANT
Third generation Power MOSFETs from Vishay utilize
advanced processing techniques to achieve extermely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient reliable device for use in a wide
variety of applications.
The D2PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and lowest possible on-resistance
in any existing surface mount package. The D2PAK is
suitable for high current applications because of its low
internal connection resistance and can dissipate up to 2.0 W
in a typical surface mount application.
The through-hole version (IRLZ44L/SiHLZ44L) is available
for low-profile applications.
D2PAK (TO-263)
G
G
Available
RoHS*
DESCRIPTION
D
I2PAK (TO-262)
Advanced Process Technology
Surface Mount (IRLZ14S/SiHLZ14S)
Low-Profile Through-Hole (IRLZ14L/SiHLZ14L)
175 °C Operating Temperature
Fast Switching
Lead (Pb)-free Available
D
S
S
N-Channel MOSFET
ORDERING INFORMATION
D2PAK (TO-263)
IRLZ14SPbF
SiHLZ14S-E3
IRLZ14S
SiHLZ14S
Package
Lead (Pb)-free
SnPb
D2PAK (TO-263)
IRLZ14STRRPbFa
SiHLZ14STR-E3a
IRLZ14TRRa
SiHLZ14TRa
I2PAK (TO-262)
IRLZ14L
SiHLZ14L
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
VDS
VGS
60
± 10
10
7.2
40
0.29
68
43
3.7
4.5
- 55 to + 175
300d
Drain-Source Voltagee
Gate-Source Voltage
Continuous Drain Current
VGS at 5 V
TC = 25 °C
TC = 100 °C
Currenta, e
IDM
Pulsed Drain
Linear Derating Factor
Single Pulse Avalanche Energyb, e
Maximum Power Dissipation
ID
EAS
TC = 25 °C
TA = 25 °C
dV/dtc, e
PD
dV/dt
Peak Diode Recovery
Operating Junction and Storage Temperature Range
TJ, Tstg
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 790 µH, RG = 25 Ω, IAS = 10 A (see fig. 12).
c. ISD ≤ 10 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 175 °C.
d. 1.6 mm from case.
e. Uses IRLZ14/SiHLZ14 data and test conditions.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 90414
S-Pending-Rev. A, 21-Jul-08
WORK-IN-PROGRESS
UNIT
V
A
W/°C
mJ
W
V/ns
°C
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IRLZ14S, IRLZ14L, SiHLZ14S, SiHLZ14L
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mount)a
PARAMETER
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
3.5
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
60
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.07
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
1.0
-
2.0
V
Gate-Source Leakage
IGSS
VGS = ± 10 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 60 V, VGS = 0 V
-
-
25
VDS = 48 V, VGS = 0 V, TJ = 150 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
VGS = 5 V
ID = 6.0 Ab
-
-
0.2
VGS = 4 V
Ab
-
-
0.28
3.5
-
-
-
400
-
-
170
-
-
42
-
ID = 5.0
VDS = 25 V, ID = 6.0 A
µA
Ω
S
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 5 V
ID = 10 A, VDS = 48 V,
see fig. 6 and 13b
-
-
8.4
-
-
3.5
pF
nC
Gate-Drain Charge
Qgd
-
-
6.0
Turn-On Delay Time
td(on)
-
9.3
-
-
110
-
-
17
-
-
26
-
-
7.5
-
-
-
10
-
-
40
-
-
1.6
-
93
130
ns
-
340
650
nC
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Internal Source Inductance
LS
VDD = 30 V, ID = 10 A,
RG = 12 Ω, RD = 2.8 Ω, see fig. 10b
Between lead, and center of die contact
ns
nH
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 10 A, VGS = 0 Vb
TJ = 25 °C, IF = 10 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 90414
S-Pending-Rev. A, 21-Jul-08
IRLZ14S, IRLZ14L, SiHLZ14S, SiHLZ14L
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 90414
S-Pending-Rev. A, 21-Jul-08
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IRLZ14S, IRLZ14L, SiHLZ14S, SiHLZ14L
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 90414
S-Pending-Rev. A, 21-Jul-08
IRLZ14S, IRLZ14L, SiHLZ14S, SiHLZ14L
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
- VDD
5V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 90414
S-Pending-Rev. A, 21-Jul-08
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IRLZ14S, IRLZ14L, SiHLZ14S, SiHLZ14L
Vishay Siliconix
L
VDS
VDS
Vary tp to obtain
required IAS
tp
VDD
D.U.T.
RG
+
-
I AS
V DD
VDS
5V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 90414
S-Pending-Rev. A, 21-Jul-08
IRLZ14S, IRLZ14L, SiHLZ14S, SiHLZ14L
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?90414.
Document Number: 90414
S-Pending-Rev. A, 21-Jul-08
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
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otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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