IRF IRS2153DPBF Self-oscillating half-bridge driver ic Datasheet

Data Sheet No. PD60238 revE
IRS2153(1)D(S)PbF
SELF-OSCILLATING HALF-BRIDGE DRIVER IC
Features
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Product Summary
Integrated 600 V half-bridge gate driver
CT, RT programmable oscillator
15.4 V Zener clamp on VCC
Micropower startup
Non-latched shutdown on CT pin (1/6th VCC)
Internal bootstrap FET
Excellent latch immunity on all inputs and outputs
+/- 50 V/ns dV/dt immunity
ESD protection on all pins
8-lead SOIC or PDIP package
Internal deadtime
Description
The IRS2153(1)D is based on the popular IR2153 selfoscillating half-bridge gate driver IC using a more
advanced silicon platform, and incorporates a high
voltage half-bridge gate driver with a front end oscillator
similar to the industry standard CMOS 555 timer. HVIC
and latch immune CMOS technologies enable rugged
monolithic construction. The output driver features a high
pulse current buffer stage designed for minimum driver
cross-conduction. Noise immunity is achieved with low
di/dt peak of the gate drivers.
VOFFSET
600 V Max
Duty cycle
50%
Driver source/sink
current
180 mA/260 mA typ.
Vclamp
15.4 V typ.
Deadtime
1.1 µs typ. (IRS2153D)
0.6 µs typ. (IRS21531D)
Package
PDIP8
IRS2153(1)DPbF
SO8
IRS2153(1)DSPbF
Typical Connection Diagram
+ AC Rectified Line
RVCC
RT
2
RT
CT
CVCC
3
CT
COM
8
1
4
IRS2153(1)D
VCC
7
6
VB
CBOOT
HO
MHS
L
VS
RL
5
LO
MLS
- AC Rectified Line
1
IRS2153(1)D
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead.
The thermal resistance and power dissipation ratings are measured under board mounted and still air
conditions.
Parameter
Definition
Symbol
Min.
Max.
-0.3
625
VB
High side floating supply voltage
VS
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS – 0.3
VB + 0.3
VLO
Low side output voltage
-0.3
VCC + 0.3
IRT
RT pin current
-5
5
VRT
RT pin voltage
-0.3
VCC + 0.3
VCT
CT pin voltage
-0.3
VCC + 0.3
ICC
Supply current (Note 1)
Maximum allowable current at LO and HO due to external
power transistor Miller effect.
Allowable offset voltage slew rate
---
20
-500
500
-50
50
IOMAX
dVS/dt
PD
Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin DIP
---
1.0
PD
Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin SOIC
---
0.625
RthJA
Thermal resistance, junction to ambient, 8-Pin DIP
---
85
RthJA
Thermal resistance, junction to ambient, 8-Pin SOIC
---
128
TJ
Junction temperature
-55
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
---
300
Units
V
mA
V
mA
V/ns
W
ºC/W
ºC
Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal
breakdown voltage of 15.4 V. Please note that this supply pin should not be driven by a DC, low
impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
2
IRS2153(1)D
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Parameter
Definition
Symbol
Min.
Max.
VCC - 0.7
VCLAMP
-3.0 (Note 2)
600
Units
VBS
High side floating supply voltage
VS
Steady state side floating supply offset voltage
VCC
Supply voltage
VCCUV+ +0.1 V
VCC CLAMP
ICC
Supply current
(Note 3)
5
mA
TJ
Junction temperature
-40
125
ºC
V
Note 2: It is recommended to avoid output switching conditions where the negative-going spikes at the VS
node would decrease VS below ground by more than -5 V.
Note 3: Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6 V zener diode
clamping the voltage at this pin.
Recommended Component Values
Parameter
Component
Symbol
Min.
Max.
Units
RT
Timing resistor value
1
---
kΩ
CT
CT pin capacitor value
330
---
pF
VBIAS (VCC, VBS) = 14 V, VS=0 V and TA = 25 °C, CLO = CHO = 1 nF.
Frequency vs. RT
1,000,000
CT Values
Frequency (Hz)
100,000
330pf
470pF
10,000
1nF
2.2nF
1,000
4.7nF
10nF
100
10
1,000
10,000
100,000
1,000,000
RT (Ohm)
For further information, see Fig. 12.
3
IRS2153(1)D
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF, VS=0 V and TA = 25 °C unless otherwise specified. The output voltage and current (VO and IO) parameters are
referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
Low Voltage Supply Characteristics
VCCUV+
Rising VCC undervoltage lockout threshold
10.0
11.0
12.0
VCCUV-
Falling VCC undervoltage lockout threshold
8.0
9.0
10.0
VCC undervoltage lockout hysteresis
1.6
2.0
2.4
Micropower startup VCC supply current
---
130
170
IQCC
Quiescent VCC supply current
---
800
1000
ICC
VCC supply current
---
1.8
---
mA
RT = 36.9 kΩ
14.4
15.4
16.8
V
ICC = 5 mA
Quiescent VBS supply current
---
60
80
µA
VBSUV+
VBS supply undervoltage positive going
threshold
8.0
9.0
9.5
VBSUV-
VBS supply undervoltage negative going
threshold
7.0
8.0
9.0
Offset supply leakage current
---
---
50
18.4
19.0
19.6
88
93
100
RT pin duty cycle
---
50
---
CT pin current
---
0.02
1.0
µA
mA
VCCUVHYS
IQCCUV
VCC CLAMP
VCC zener clamp voltage
V
µA
VCC ≤ VCCUV-
Floating Supply Characteristics
IQBS
ILK
V
µA
VB = VS = 600 V
Oscillator I/O Characteristics
fOSC
d
ICT
Oscillator frequency
kHz
%
RT = 36.5 kΩ
RT = 7.15 kΩ
fo < 100 kHz
ICTUV
UV-mode CT pin pulldown current
0.20
0.30
0.6
VCT+
Upper CT ramp voltage threshold
---
9.32
---
VCT-
Lower CT ramp voltage threshold
---
4.66
---
VCTSD
CT voltage shutdown threshold
2.2
2.3
2.4
VRT+
High-level RT output voltage, VCC - VRT
---
10
50
IRT = -100 µA
---
100
300
IRT = -1 mA
VRT-
Low-level RT output voltage
---
10
50
IRT = 100 µA
---
100
300
IRT = 1 mA
VRTUV
UV-mode RT output voltage
---
0
100
VRTSD
---
10
50
---
100
300
SD-mode RT output voltage, VCC - VRT
VCC = 7 V
V
VCC ≤ VCCUVmV
IRT = -100 µA,
VCT = 0 V
IRT = -1 mA,
VCT = 0 V
4
IRS2153(1)D
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF, VS=0 V and TA = 25 °C unless otherwise specified. The output voltage and current (VO and IO)
parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
Gate Driver Output Characteristics
VOH
High-level output voltage
---
VCC
---
VOL
Low-level output voltage
---
COM
---
VOL_UV
UV-mode output voltage
---
COM
---
tr
Output rise time
---
120
220
tf
Output fall time
---
50
80
tsd
Shutdown propagation delay
---
350
---
td
Output deadtime (HO or LO) (IRS2153D)
0.65
1.1
1.75
µs
td
Output deadtime (HO or LO) (IRS21531D)
0.35
0.6
0.85
µs
IO+
Output source current
---
180
---
IO-
Output sink current
---
260
---
IO = 0 A
V
IO = 0 A,
VCC ≤ VCCUVns
mA
Bootstrap FET Characteristics
VB_ON
VB when the bootstrap FET is on
---
13.7
---
IB_CAP
VB source current when FET is on
40
55
---
IB_10V
VB source current when FET is on
10
12
---
V
mA
CBS=0.1 uF
VB=10 V
5
IRS2153(1)D
Lead Definitions
RT
CT
COM
8
1
2
3
4
IRS2153(1)D
VCC
7
6
5
VB
HO
VS
LO
Lead
Description
Symbol
VCC
Logic and internal gate drive supply voltage
RT
Oscillator timing resistor input
CT
Oscillator timing capacitor input
COM
IC power and signal ground
LO
Low-side gate driver output
VS
High voltage floating supply return
HO
High-side gate driver output
VB
High side gate driver floating supply
6
IRS2153(1)D
Functional Block Diagram
RT 2
R
HV
LEVEL
SHIFT
+
R
R
+
-
S
Q
Q
+
R/2
S Q
R1
R2
R
7
HO
6
VS
S
PULSE
GEN
VB
Q
PULSE
FILTER
BOOTSTRAP
DRIVE
DEAD
TIME
R/2
CT 3
DEAD
TIME
8
15.4V
DELAY
1 VCC
5
LO
4
COM
M1
UV
DETECT
7
IRS2153(1)D
Timing Diagram
Operating Mode
VCCUV+
VCC
Fault Mode:
CT <1/6*VCC
2/3 VCC
VCT
1/3 VCC
1/6 VCC
VCC
LO
DT
VCC
HO
DT
VCC
VRT
IRT
Switching Time Waveform
Deadtime Waveform
90%
tr
tf
LO
10%
DTLO
DTHO
90%
HO
HO
LO
10%
90%
10%
8
IRS2153(1)D
Bootstrap MOSFET
Functional Description
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the state
the IC is in when VCC is below the turn-on threshold of the IC. The
IRS2153(1)D under voltage lock-out is designed to maintain an
ultra low supply current of less than 170 µA, and to guarantee the
IC is fully functional before the high and low side output drivers
are activated. During under voltage lock-out mode, the high and
low-side driver outputs HO and LO are both low.
Supply voltage
+ AC Rectified Line
RVCC
VCC
8
RT
2
RT
CT
3
CVCC
CT
COM
4
IRS2153(1)D
1
7
6
VB
CBOOT
MHS
HO
L
VS
The internal bootstrap FET and supply capacitor (CBOOT) comprise
the supply voltage for the high side driver circuitry. The internal
boostrap FET only turns on when LO is high. To guarantee that
the high-side supply is charged up before the first pulse on pin
HO, the first pulse from the output drivers comes from the LO pin.
Normal operating mode
Once the VCCUV+ threshold is passed, the MOSFET M1 opens, RT
increases to approximately VCC (VCC-VRT+) and the external CT
capacitor starts charging. Once the CT voltage reaches VCT(about 1/3 of VCC), established by an internal resistor ladder, LO
turns on with a delay equivalent to the deadtime (td). Once the CT
voltage reaches VCT+ (approximately 2/3 of VCC), LO goes low, RT
goes down to approximately ground (VRT-), the CT capacitor
discharges and the deadtime circuit is activated. At the end of the
deadtime, HO goes high. Once the CT voltage reaches VCT-, HO
goes low, RT goes high again, the deadtime is activated. At the
end of the deadtime, LO goes high and the cycle starts over
again.
The following equation provides the oscillator frequency:
RL
5
MLS
LO
f ~
1
1.453 × RT × CT
- AC Rectified Line
Fig. 1 Typical Connection Diagram
Fig. 1 shows an example of supply voltage. The start-up capacitor
(CVCC) is charged by current through supply resistor (RVCC) minus
the start-up current drawn by the IC. This resistor is chosen to
provide sufficient current to supply the IRS2153(1)D from the DC
bus. CVCC should be large enough to hold the voltage at Vcc
above the UVLO threshold for one half cycle of the line voltage as
it will only be charged at the peak, typically 0.1 uF. It will be
necessary for RVCC to dissipate around 1 W.
This equation can vary slightly from actual measurements due to
internal comparator over- and under-shoot delays. For a more
accurate determination of the output frequency, the frequency
characteristic curves should be used (RT vs. Frequency, page 3).
Shut-down
If CT is pulled down below VCTSD (approximately 1/6 of VCC) by
an external circuit, CT doesn’t charge up and oscillation stops.
LO is held low and the bootstrap FET is off. Oscillation will
resume once CT is able to charge up again to VCT-.
The use of a two diode charge pump made of DC1, DC2 and
CVS (Fig. 2) from the half bridge (VS) is also possible however
the above approach is simplest and the dissipation in RVCC should
not be unacceptably high.
+ AC Rectified Line
RVCC
RT
2
RT
CT
CVCC
3
CT
COM
8
1
4
IRS2153(1)D
VCC
7
VB
CBOOT
HO
MHS
DC2
6
L
VS
CVS
5
LO
RL
MLS
DC1
- AC Rectified Line
Fig. 2 Charge pump circuit
The supply resistor (RVCC) must be selected such that enough
supply current is available over all operating conditions.
Once the capacitor voltage on VCC reaches the start-up threshold
VCCUV+, the IC turns on and HO and LO begin to oscillate.
9
19
100
18.8
98
Frequency (kHz)
Frequency (kHz)
IRS2153(1)D
18.6
18.4
96
94
92
18.2
90
-25
18
11
12
13
14
15
0
25
16
50
75
100
125
Temperature(C)
VCC(V)
FREQ vs VCC
FREQ vs TEMP
Fig. 4
1.25
1.3
1.15
1.2
1.05
DT(uS)
DT(uS)
Fig. 3
1.4
1.1
0.95
0.85
1
0.9
11
12
13
14
15
16
0.75
-25
0
25
50
75
100
125
Temperature(C)
VCC(V)
DT vs TEMP
DT vs VCC
Fig. 5 (IRS2153D)
Fig. 6 (IRS2153D)
17
90
80
VCC (V)
Temperature(C)
70
60
50
40
16
30
20
10
15
0
-25
20
70
120
Frequency(kHz)
0
25
50
75
100
125
Temperature (°C)
VCC CLAMP vs TEMP
Tj vs. Frequency (SOIC)
Fig. 7
Fig. 8
10
IRS2153(1)D
300
300
200
150
IsinkLO
250
IsinkHO
LO Current (mA)
HOCurrent (mA)
250
IsourceHO
100
200
150
IsourceLO
100
50
50
0
-25
0
25
50
75
100
0
-25
125
0
25
Temperature(C)
50
75
100
125
Temperature(C)
IsourceHO,IsinkHO vs Temp
IsourceLO,IsinkLO vs Temp
Fig. 9
Fig. 10
80
VOH_HO vs. Frequency
With External BS diode
IB_CAP
60
50
16
40
14
VOH_HO (V)
IBS_10V
20
10
0
-25
No external BS diode
12
30
0
25
50
75
100
10
8
6
4
125
2
Temperature(C)
0
0
IBCAP, IBS10V vs TEMP
50
100
T=25°C, VS=0V, CHO = 1nF
Fig. 11
150
200
250
300
350
400
Frequency (kHz)
Fig. 12
VOH_HO vs . Fre que ncy vs . Te m p
VCC=14V, CHO=1nF, VS=0V
14
12
VOH_HO(V)
IB_CAP, IBS_10V (mA)
70
10
8
6
4
2
0
hz
K
46
.
1
K
20
K
50
K
75
0K
10
5K
12
0K
15
0K
20
Fre que ncy (k Hz)
T=-25c
T=25c
T=75c
T=125c
Fig. 13
11
IRS2153(1)D
IRS2153(1)DPbF
IRS2153(1)DSPbF
12
IRS2153(1)D
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
11.70
12.30
D
5.45
5.55
E
6.30
6.50
F
5.10
5.30
G
1.50
n/a
H
1.50
1.60
8SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.46
0.484
0.214
0.218
0.248
0.255
0.200
0.208
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
13
IRS2153(1)D
PART MARKING INFORMATION
ORDER INFORMATION
8-Lead PDIP IRS2153DPbF
8-Lead PDIP IRS21531DPbF
8-Lead SOIC IRS2153DSPbF
8-Lead SOIC IRS21531DSPbF
8-Lead SOIC Tape & Reel IRS2153DSTRPbF
8-Lead SOIC Tape & Reel IRS21531DSTRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com <http://www.irf.com>
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/27/2006
14
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