ISSI IS61C5128AL 512k x 8 high-speed cmos static ram Datasheet

IS61C5128AL/AS
IS64C5128AL/AS
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS61/64C5128AL)
• High-speed access time: 10ns, 12 ns
• Low Active Power: 150 mW (typical)
• Low Standby Power: 10 mW (typical)
CMOS standby
LOW POWER: (IS61/64C5128AS)
• High-speed access time: 25ns
• Low Active Power: 75 mW (typical)
• Low Standby Power: 1 mW (typical)
CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Available in 36-pin SOJ (400-mil), 32-pin
sTSOP-I, 32-pin SOP, 44-pin TSOP-II and 32pin TSOP-II packages
• Commercial, Industrial and Automotive temperature ranges available
• Lead-free available
MARCH 2008
DESCRIPTION
The ISSI IS61C5128AL/AS and IS64C5128AL/AS are highspeed, 4,194,304-bit static RAMs organized as 524,288
words by 8 bits. They are fabricated using ISSI's highperformance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61C5128AL/AS and IS64C5128AL/AS are packaged
in the JEDEC standard 36-pin SOJ (400-mil), 32-pin sTSOPI, 32-pin SOP, 44-pin TSOP-II and 32-pin TSOP-II packages
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CE
OE
CONTROL
CIRCUIT
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
1
IS61C5128AL/AS
IS64C5128AL/AS
HIGH SPEED (IS61/64C5128AL) PIN CONFIGURATION
36-Pin SOJ (400-mil)
44-Pin TSOP (Type II)
A0
1
36
NC
A1
2
35
A18
A2
3
34
A17
A3
4
33
A16
A4
5
32
A15
CE
6
31
OE
I/O0
7
30
I/O7
I/O1
8
29
I/O6
VDD
9
28
GND
GND
10
27
VDD
I/O2
11
26
I/O5
I/O3
12
25
I/O4
WE
13
24
A14
A5
14
23
A13
A6
15
22
A12
A7
16
21
A11
A8
17
20
A10
A9
18
19
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
PIN DESCRIPTIONS
2
A0-A18
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Bidirectional Ports
VDD
Power
GND
Ground
NC
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS
IS64C5128AL/AS
LOW POWER (IS61/64C5128AS) PIN CONFIGURATION
32-pin sTSOP (TYPE I)
A11
A9
A8
A13
WE
A18
A15
VDD
A17
A16
A14
A12
A7
A6
A5
A4
32-pin SOP
32-pin TSOP (TYPE II)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A18
Address Inputs
CE
Chip Enable 1 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
3
IS61C5128AL/AS
IS64C5128AL/AS
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
WE
CE
OE
I/O0-I/O7
I/O PIN
VDD Current
X
H
H
L
H
L
L
L
X
H
L
X
High-Z
High-Z
DOUT
DIN
ISB1, ISB2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VDD + 0.5
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
Com.
Ind.
Auto.
–1
–2
–5
1
2
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD
Outputs Disabled
Com.
Ind.
Auto.
–1
–2
–5
1
2
5
µA
Note:
4
1. VIL = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS
IS64C5128AL/AS
OPERATING RANGE: HIGH SPEED OPTION (IS61/64C5128AL)
Range
Commercial
Ambient Temperature
0°C to +70°C
VDD
5V ± 10%
Speed (ns)
10
Industrial
-40°C to +85°C
5V ± 10%
10
Automotive
-40°C to +125°C
5V ± 10%
12
OPERATING RANGE: LOW POWER OPTION (IS61/64C5128AS)
Range
Commercial
Ambient Temperature
0°C to +70°C
VDD
5V ± 10%
Speed (ns)
25
Industrial
-40°C to +85°C
5V ± 10%
25
Automotive
-40°C to +125°C
5V ± 10%
25
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
5
IS61C5128AL/AS
IS64C5128AL/AS
HIGH SPEED OPTION (IS61/64C5128AL)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10 ns
Min. Max.
-12 ns
Min. Max.
Symbol Parameter
Test Conditions
ICC1
VDD Operating
Supply Current
VDD = VDD MAX., CE = VIL
IOUT = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
45
50
55
—
—
—
45
50
55
mA
ICC2
VDD Dynamic Operating
Supply Current
VDD = VDD MAX., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
Auto.
typ.(2)
—
—
—
50
55
70
—
—
—
45
50
60
mA
30
Unit
25
ISB1
TTL Standby Current
(TTL Inputs)
VDD = VDD MAX.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
15
20
30
—
—
—
15
20
30
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = VDD MAX.,
CE ≤ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
Auto.
typ.(2)
—
—
—
8
12
20
—
—
—
8
12
20
mA
2
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25% and not 100% tested.
LOW POWER OPTION (IS61/64C5128AS)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
Average operating
Current
CE = VIL, VDD = Max.
I OUT= 0 mA, f= 0
Com.
Ind.
Auto.
—
—
—
10
15
20
mA
ICC1
VDD Dynamic Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
Auto.
typ.(2)
—
—
—
25
30
40
mA
15
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL, CE ≥ VIH,
f=0
Com.
Ind.
Auto.
—
—
—
1
1.5
2
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V,
or VIN ≤ VSS + 0.2V, f = 0
Com.
Ind.
Auto.
typ.
—
—
—
0.8
0.9
2
mA
0.2
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25% and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS
IS64C5128AL/AS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
tRC
tAA
tOHA
tACE
tDOE
tHZOE(2)
tLZOE(2)
tHZCE(2)
tLZCE(2)
Parameter
Read Cycle Time
-10
Min. Max.
10
—
-12
Min. Max.
12
—
-25
Min. Max.
25
—
Unit
ns
Address Access Time
—
10
—
12
—
25
ns
Output Hold Time
3
—
3
—
3
—
ns
CE Access Time
—
10
—
12
—
25
ns
OE Access Time
—
5
—
6
—
15
ns
OE to High-Z Output
0
5
0
6
0
8
ns
OE to Low-Z Output
0
—
0
—
2
—
ns
CE to High-Z Output
0
5
0
6
0
8
ns
CE to Low-Z Output
2
—
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0
to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
255 Ω
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
5 pF
Including
jig and
scope
255 Ω
Figure 2
7
IS61C5128AL/AS
IS64C5128AL/AS
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
CE
t LZOE
t ACS
t HZCS
t LZCS
DOUT
HIGH-Z
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS
IS64C5128AL/AS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter
-10
Min. Max.
-12
Min. Max.
-25
Min. Max.
Unit
tWC
Write Cycle Time
10
—
12
—
25
—
ns
tSCE
CE to Write End
7
—
9
—
18
—
ns
tAW
Address Setup Time
to Write End
7
—
9
—
18
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
ns
tPWE1
WE Pulse Width (OE =High)
7
—
9
—
15
—
ns
tPWE2
WE Pulse Width (OE=Low)
7
—
9
—
15
—
ns
tSD
Data Setup to Write End
6
—
6
—
15
—
ns
Data Hold from Write End
0
—
0
—
0
—
ns
WE LOW to High-Z Output
—
6
—
6
—
15
ns
tLZWE(2) WE HIGH to Low-Z Output
3
—
3
—
5
—
ns
tHD
tHZWE
(2)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or
falling edge of the signal that terminates the write.
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Rev. B
03/04/2008
9
IS61C5128AL/AS
IS64C5128AL/AS
AC WAVEFORMS
WE Controlled)(1,2)
WRITE CYCLE NO. 1 (WE
t WC
VALID ADDRESS
ADDRESS
t SA
t SCS
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
10
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Rev. B
03/04/2008
IS61C5128AL/AS
IS64C5128AL/AS
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
t HZWE
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
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Rev. B
03/04/2008
11
IS61C5128AL/AS
IS64C5128AL/AS
DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61/64C5128AL)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VDR
VDD for Data Retention
See Data Retention Waveform
2.9
5.5
V
IDR
Data Retention Current
VDD = 2.9V, CE ≥ VDD – 0.2V
VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V
—
—
—
8
10
15
mA
Com.
Ind.
Auto.
typ. (1)
1
tSDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
—
ns
Note:
1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE
CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
4.5V
VDR
CE
GND
12
CE ≥ VDD - 0.2V
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Rev. B
03/04/2008
IS61C5128AL/AS
IS64C5128AL/AS
DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61/64C5128AS)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VDR
VDD for Data Retention
See Data Retention Waveform
2.9
5.5
V
IDR
Data Retention Current
VDD = 2.9V, CE ≥ VDD – 0.2V
VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V
—
—
—
0.8
0.9
2
mA
Com.
Ind.
Auto.
typ. (1)
0.2
tSDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
—
ns
Note:
1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE
CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
4.5V
VDR
CE
GND
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Rev. B
03/04/2008
CE ≥ VDD - 0.2V
13
IS61C5128AL/AS
IS64C5128AL/AS
HIGH SPEED (IS61/64C5128AL)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
10
Order Part No.
Package
IS61C5128AL-10KI
IS61C5128AL-10KLI
IS61C5128AL-10TI
IS61C5128AL-10TLI
400-mil Plastic SOJ
400-mil Plastic SOJ, Lead-free
44-pin TSOP-II
44-pin TSOP-II, Lead-free
Automotive Range: –40°C to +125°C
Speed (ns)
12
Order Part No.
Package
IS64C5128AL-12KA3
IS64C5128AL-12TA3
IS64C5128AL-12TLA3
400-mil Plastic SOJ
44-pin TSOP-II
44-pin TSOP-II, Lead-free
LOW POWER (IS61/64C5128AS)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
25
14
Order Part No.
Package
IS61C5128AS-25QI
IS61C5128AS-25QLI
IS61C5128AS-25HI
IS61C5128AS-25HLI
IS61C5128AS-25TI
IS61C5128AS-25TLI
450-mil Plastic SOP
450-mil Plastic SOP, Lead-free
32-pin STSOP-I
32-pin STSOP-I, Lead-free
32-pin TSOP-II
32-pin TSOP-II, Lead-free
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Rev. B
03/04/2008
PACKAGING INFORMATION
450-mil Plastic SOP
Package Code: Q (32-pin)
N
E1
E
1
D
SEATING PLANE
A
S
MILLIMETERS
Symbol
No. Leads
A
A1
B
C
D
E
E1
e
L
α
S
Min.
L
B
e
A1
INCHES
Max.
Min.
Max.
32
—
3.00
0.10
—
0.36
0.51
0.15
0.30
20.14
20.75
13.87
14.38
11.18
11.43
1.27 BSC
0.58
0.99
0°
10°
—
0.86
—
0.118
0.004
—
0.014
0.020
0.006
0.012
0.793
0.817
0.546
0.566
0.440
0.450
0.050 BSC
0.023
0.039
0°
10°
—
0.034
α
C
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
N
Notes:
1. Controlling dimension:
millimeters.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
N/2+1
E1
1
E
N/2
SEATING PLANE
D
b
A
C
A2
e
Symbol
No. Leads
A
A1
A2
B
b
C
D
E
E1
E2
e
B
Millimeters
Inches
Min Max
Min
Max
(N)
28
3.25 3.75
0.128 0.148
0.64 —
0.025
—
2.08 —
0.082
—
0.38 0.51
0.015 0.020
0.66 0.81
0.026 0.032
0.18 0.33
0.007 0.013
18.29 18.54
0.720 0.730
11.05 11.30
0.435 0.445
10.03 10.29
0.395 0.405
9.40 BSC
0.370 BSC
1.27 BSC
0.050 BSC
A1
E2
Millimeters
Min Max
Inches
Min Max
Millimeters
Min Max
32
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
20.82 21.08
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
0.820 0.830
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
23.37 23.62
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
Inches
Min Max
36
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
0.920 0.930
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
Millimeters
Inches
Symbol Min Max
Min
Max
No. Leads (N)
40
A
3.25 3.75
0.128 0.148
A1
0.64 —
0.025
—
A2
2.08 —
0.082
—
B
0.38 0.51
0.015 0.020
b
0.66 0.81
0.026 0.032
C
0.18 0.33
0.007 0.013
D
25.91 26.16
1.020 1.030
E
11.05 11.30
0.435 0.445
E1
10.03 10.29
0.395 0.405
E2
9.40 BSC
0.370 BSC
e
1.27 BSC
0.050 BSC
Millimeters
Min Max
Inches
Min Max
Millimeters
Min
Max
42
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
27.18 27.43
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
1.070 1.080
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
28.45 28.70
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
Inches
Min
Max
44
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
1.120 1.130
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
Plastic STSOP - 32 pins
Package Code: H (Type I)
A2
A
A1
1
N
E
b
e
D1
S
SEATING PLANE
D
L
Plastic STSOP (H - Type I)
Millimeters
Inches
Symbol Min Max
Min
Max
Ref. Std.
N
32
A
—
1.25
—
0.049
A1
0.05
—
0.002
—
A2
0.95 1.05
0.037
0.041
b
0.17 0.23
0.007
0.009
C
0.14 0.16
0.0055 0.0063
D
13.20 13.60
0.520
0.535
D1 11.70 11.90
0.461
0.469
E
7.90 8.10
0.311
0.319
e
0.50 BSC
0.020 BSC
L
0.30 0.70
0.012
0.028
S
0.28 Typ.
0.011 Typ.
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197H32 Rev. B 04/21/03
α
C
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1
1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
E
N/2
D
SEATING PLANE
A
ZD
.
b
e
Symbol
Ref. Std.
No. Leads
A
A1
b
C
D
E1
E
e
L
ZD
α
Millimeters
Min
Max
Inches
Min
Max
(N)
32
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.52
0.012 0.020
0.12 0.21
0.005 0.008
20.82 21.08
0.820 0.830
10.03 10.29
0.391 0.400
11.56 11.96
0.451 0.466
1.27 BSC
0.050 BSC
0.40 0.60
0.016 0.024
0.95 REF
0.037 REF
0°
5°
0°
5°
L
α
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min Max
44
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.45
0.012 0.018
0.12 0.21
0.005 0.008
18.31 18.52
0.721 0.729
10.03 10.29
0.395 0.405
11.56 11.96
0.455 0.471
0.80 BSC
0.032 BSC
0.41 0.60
0.016 0.024
0.81 REF
0.032 REF
0°
5°
0°
5°
Millimeters
Min
Max
C
Inches
Min
Max
50
—
1.20
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
0.88 REF
0°
5°
—
0.047
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
0.035 REF
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
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