ISSI IS61LF6432A-8.5TQI 64k x 32, 64kx36 synchronous flow-through static ram Datasheet

IS61LF6436A
IS61LF6432A
ISSI
®
64K x 32, 64Kx36
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
OCTOBER 2005
DESCRIPTION
FEATURES
The ISSI IS61LF6432A and IS61LF6436A are high-speed,
low-power synchronous static RAM designed to provide a
burstable, high-performance, memory. IS61LF6432A is
organized as 65,536 words by 32 bits. IS61LF6436A is
organized as 65,536 words by 36 bits. They are fabricated
with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP package
• Power Supply:
+3.3V VDD
+3.3V or 2.5V VDDQ
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
• Industrial Temperature Available:
(-40oC to +85oC)
• Lead-free available
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BWa controls DQa, BWb controls DQb, BWc controls DQc,
BWd controls DQd, conditioned by BWE being LOW. A
LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61LF6432A/36A and controlled by the
ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
Parameter
8.5
Unit
tKQ
Clock Access Time
8.5
ns
tKC
Cycle Time
11
ns
Frequency
90
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
1
IS61LF6436A
IS61LF6432A
ISSI
®
BLOCK DIAGRAM
MODE
CLK
A0'
Q0
CLK
BINARY
COUNTER
ADV
CE
ADSC
ADSP
A1'
Q1
64Kx32;
64Kx36
MEMORY ARRAY
CLR
A0, A1
17/18
A
14
D
16
Q
ADDRESS
REGISTER
CE
CLK
32, 36
GW
BWE
BW(a-d)
x32/x36: a-d
D
32, 36
Q
DQ(a-d)
BYTE WRITE
REGISTERS
CLK
CE
4
Q
CE2
D
CE2
ENABLE
REGISTER
32, 36
INPUT
REGISTERS
CLK
DQa - DQd
OE
CE
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
IS61LF6436A
IS61LF6432A
ISSI
®
PIN CONFIGURATION
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
Vss
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
NC
MODE
A
A
A
A
A1
A0
NC
NC
Vss
VDD
NC
NC
A
A
A
A
A
A
NC
NC
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
NC
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
NC
64K x 32
PIN DESCRIPTIONS
A0, A1
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
GW
CE, CE2, CE2
OE
DQa-DQd
MODE
VDD
Vss
VDDQ
ZZ
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
or 2.5V
Snooze Enable
3
IS61LF6436A
IS61LF6432A
ISSI
®
PIN CONFIGURATION
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
Vss
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
DQPc
DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
MODE
A
A
A
A
A1
A0
NC
NC
Vss
VDD
NC
NC
A
A
A
A
A
A
NC
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
NC
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
64K x 36
PIN DESCRIPTIONS
A0, A1
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
4
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2, CE2
OE
DQa-DQd
MODE
VDD
Vss
VDDQ
ZZ
DQPa-DQPd
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V or
2.5V
Snooze Enable
Parity Data I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
IS61LF6436A
IS61LF6432A
ISSI
®
TRUTH TABLE
Operation
Address
CE
Used
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE2
CE2
H
L
L
X
X
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
X
L
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
WRITE
OE
DQ
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Q
D
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
BWE
BWa
BWb
BWc
BWd
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
5
IS61LF6436A
IS61LF6432A
ISSI
®
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TSTG
PD
IOUT
VIN, VOUT
VIN
VDD
Parameter
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to Vss for I/O Pins
Voltage Relative to Vss for
for Address and Control Inputs
Voltage on VDD Supply Relative to Vss
Value
–55 to +150
1.6
100
–0.5 to VDDQ + 0.3
–0.5 to VDD + 0.5
Unit
°C
W
mA
V
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
IS61LF6436A
IS61LF6432A
ISSI
®
OPERATING RANGE
Range
Industrial
Ambient Temperature
VDD
3.3V (I/O)
VDDQ
2.5V (I/O)
VDDQ
–40°C to +85°C
3.3V, +10%, –5%
3.3V, +10%, –5%
2.5V + 5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol
VOH
Parameter
OutputHIGHVoltage
VOL
OutputLOWVoltage
VIH
VIL
ILI
ILO
Input HIGH Voltage
Input LOW Voltage
InputLeakageCurrent
OutputLeakageCurrent
Test Conditions
IOH = –4.0 mA (3.3V)
IOH = 1.0 mA (2.5V)
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
Vss ≤ VIN ≤ VDD
Vss ≤ VOUT ≤ VDDQ,
OE = VI
2.5V (I/O)
Min.
Max.
2.0
—
3.3V (I/O)
Min.
Max.
2.4
—
Unit
V
—
0.4
—
0.4
V
1.7
–0.3
–5
–5
VDD + 0.3
0.7
5
5
2.0
–0.3
–5
–5
VDD + 0.3
0.8
5
5
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
ICC
Parameter
AC Operating
Supply Current
ISB1
Standby Current
CMOS Input
IZZ
Sleep Mode
Test Conditions
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
Device Deselected,
VDD = Max.,
VIN ≤ VSS + 0.2V or ≥VDD – 0.2V
f=0
ZZ>VIH
IND.
8.5
Max.
150
Unit
mA
IND.
75
mA
IND.
35
mA
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to Vss, or tied to VDD.
2. The MODE pin should be tied to VDD or Vss. It exhibits ±10 µA maximum leakage current when tied to ≤ Vss + 0.2V
or ≥ VDD – 0.2V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
7
IS61LF6436A
IS61LF6432A
ISSI
®
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
ZO = 50Ω
+3.3V
Output
50Ω
OUTPUT
351 Ω
1.5V
Figure 1
8
5 pF
Including
jig and
scope
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
IS61LF6436A
IS61LF6432A
ISSI
®
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1ns
1.25V
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
ZO = 50Ω
+2.5V
Output
OUTPUT
50Ω
1538 Ω
1.25V
Figure 3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
5 pF
Including
jig and
scope
Figure 4
9
IS61LF6436A
IS61LF6432A
ISSI
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
8.5
Symbol
fMAX
tKC
(3)
(3)
tKH
Parameter
Min.
Max.
Unit
Clock Frequency
—
90
MHz
Cycle Time
11
—
ns
Clock High Time
4.5
—
ns
(3)
Clock Low Time
4.5
—
ns
(3)
Clock Access Time
—
8.5
ns
Clock High to Output Invalid
2
—
ns
Clock High to Output Low-Z
0
—
ns
Clock High to Output High-Z
2
3.5
ns
Output Enable to Output Valid
—
4.0
ns
tOEQX
Output Enable to Output Invalid
2
—
ns
tOELZ(1,2)
Output Enable to Output Low-Z
0
—
ns
tOEHZ(1,2)
tKL
tKQ
tKQX
(1)
tKQLZ(1,2)
tKQHZ
(1,2)
(3)
tOEQ
(1)
Output Disable to Output High-Z
—
5.0
ns
(3)
Address Setup Time
2
—
ns
(3)
Address Status Setup Time
2
—
ns
tAS
tSS
tWS(3)
Write Setup Time
2
—
ns
(3)
Chip Enable Setup Time
2
—
ns
(3)
Address Advance Setup Time
2
—
ns
Address Hold Time
1
—
ns
Address Status Hold Time
0.5
—
ns
tCES
tAVS
(3)
tAH
tSH(3)
tWH
(3)
Write Hold Time
0.5
—
ns
(3)
Chip Enable Hold Time
0.5
—
ns
(3)
Address Advance Hold Time
0.5
—
ns
tCEH
tAVH
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
IS61LF6436A
IS61LF6432A
ISSI
®
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC
ADV
tAS
Address
tAH
RD1
RD2
WR1
tWS
tWH
tWS
tWH
RD3
GW
BWE
tWS
tWH
WR1
BWd-BWa
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
CE2 and CE2 only sampled with ADSP or ADSC
CE2
Unselected with CE2
CE2
tOEHZ
OE
tKQ
tOEQX
DATAOUT
High-Z
2c
2d
tKQHZ
tKQHZ
High-Z
1a
tDS
Single Read
Flow-through
tDH
Single Write
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
2b
tKQX
tKQX
tKQX
tKQ
DATAIN
2a
1a
tKQLZ
tKQ
Burst Read
Unselected
11
IS61LF6436A
IS61LF6432A
ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
8.5
Symbol
Parameter
Min.
Max.
Unit
tKC(1)
Cycle Time
11
—
ns
tKH(1)
tKL
Clock High Time
4.5
—
ns
(1)
Clock Low Time
4.5
—
ns
(1)
Address Setup Time
2
—
ns
tAS
tSS(1)
Address Status Setup Time
2
—
ns
(1)
Write Setup Time
2
—
ns
(1)
Data In Setup Time
3
—
ns
tCES
Chip Enable Setup Time
2
—
ns
tAVS(1)
tWS
tDS
(1)
Address Advance Setup Time
2
—
ns
tAH
(1)
Address Hold Time
1
—
ns
tSH
(1)
Address Status Hold Time
0.5
—
ns
(1)
tDH
Data In Hold Time
1
—
ns
tWH(1)
Write Hold Time
0.5
—
ns
tCEH(1)
Chip Enable Hold Time
0.5
—
ns
Address Advance Hold Time
0.5
—
ns
(1)
tAVH
Notes:
1. Tested with load in Figure 1.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
IS61LF6436A
IS61LF6432A
ISSI
®
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
ADV must be inactive for ADSP Write tAVS
tAVH
ADV
tAS
A
tAH
WR1
WR3
WR2
tWS
tWH
tWS
tWH
tWS
tWH
GW
BWE
BWd-BWa
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
tDH
1a
BW4-BW1 only are applied to first cycle of WR2
2a
2b
2c
2d
Burst Write
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
3a
Write
Unselected
13
IS61LF6436A
IS61LF6432A
ISSI
®
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
ISB2
Current during SNOOZE MODE
ZZ ≥ Vih
—
35
mA
tPDS
ZZ active to input ignored
—
2
cycle
tPUS
ZZ inactive to input sampled
2
—
cycle
tZZI
ZZ active to SNOOZE current
—
2
cycle
tRZZI
ZZ inactive to exit SNOOZE current
0
—
ns
SNOOZE MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
IS61LF6436A
IS61LF6432A
ISSI
®
ORDERING INFORMATION
3.3V I/O OR 2.5V I/O
Industrial Range: -40°C TO +85°C
Speed (ns)
Order Part No.
Package
8.5
IS61LF6432A-8.5TQI
IS61LF6432A-8.5TQLI
TQFP
TQFP, Lead-free
8.5
IS61LF6436A-8.5TQI
IS61LF6436A-8.5TQLI
TQFP
TQFP, Lead-free
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
15
ISSI
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Thin Quad Flat Pack (TQ)
Inches
Millimeters
Min
Max
Min
Max
Millimeters
Symbol Min
Max
Ref. Std.
No. Leads (N)
100
A
—
1.60
—
0.063
A1
0.05 0.15
0.002 0.006
A2
1.35 1.45
0.053 0.057
b
0.22 0.38
0.009 0.015
D
21.90 22.10
0.862 0.870
D1
19.90 20.10
0.783 0.791
E
15.90 16.10
0.626 0.634
E1
13.90 14.10
0.547 0.555
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
L1
1.00 REF.
0.039 REF.
C
0o
7o
0o
7o
128
—
1.60
0.05 0.15
1.35 1.45
0.17 0.27
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.45 0.75
1.00 REF.
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev. D 05/08/03
Inches
Min
Max
—
0.063
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
0.018 0.030
0.039 REF.
0o
7o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.
®
Similar pages