ISSI IS61NLP12832-5B Pipeline no wait state bus sram Datasheet

IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
128K x 32, 128K x 36 and 256K x 18
PIPELINE 'NO WAIT' STATE BUS SRAM
ISSI
®
PRELIMINARY INFORMATION
OCTOBER 2000
FEATURES
DESCRIPTION
•
•
•
•
•
•
The 4 Meg 'NP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 131,072 words by 32 bits, 131,072 words
by 36 bits and 262,144 words by 18 bits, fabricated with
ISSI's advanced CMOS technology.
•
•
•
•
•
•
•
•
•
•
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address,
data and control
Interleaved or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining for TQFP
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 119 PBGA package
Single +3.3V power supply (± 5%)
NP Version: 3.3V I/O Supply Voltage
NLP Version: 2.5V I/O Supply Voltage
Industrial temperature available
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
t KC
Parameter
Clock Access Time
Cycle Time
Frequency
-150*
3.8
6.7
150
-133
4.2
7.5
133
-100
5
10
100
Units
ns
ns
MHz
*This speed available only in NP version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
11/30/00
Rev. 00C
1
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
BLOCK DIAGRAM
A [0:16] or
A [0:17]
ADDRESS
REGISTER
A2-A16 or A2-A17
MODE
A0-A1
CLK
CONTROL
LOGIC
K
CKE
WRITE
ADDRESS
REGISTER
128Kx32; 128Kx36;
256Kx18
MEMORY ARRAY
BURST
ADDRESS
COUNTER
A'0-A'1
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
K
DATA-IN
REGISTER
CE
CE2
CE2
ADV
WE
BWŸX
}
CONTROL
REGISTER
K
CONTROL
LOGIC
(X=a,b,c,d or a,b)
OUTPUT
REGISTER
BUFFER
OE
ZZ
DQa0-DQd7 or DQa0-DQb8
DQPa-DQPd
2
32, 36 or 18
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
PIN CONFIGURATION
1
2
3
4
5
6
7
VCCQ
A6
A4
NC
A8
A16
VCCQ
NC
CE2
A3
ADV
A9
CE2
NC
NC
A7
A2
VCC
A12
A15
NC
DQc1
NC
GND
NC
GND
NC
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BWc
NC
BWb
DQb4
DQb3
DQc7
DQc8
GND
WE
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BWd
NC
BWa
DQa5
DQa6
VCCQ
DQd5
GND
CKE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
NC
GND
A0
GND
NC
DQa1
NC
A5
MODE
VCC
VCC
A13
NC
NC
NC
A10
A11
A14
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
119-pin PBGA (Top View) and 100-Pin TQFP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
VCC
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
VCC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
T
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
128K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
3
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
PIN CONFIGURATION
1
2
3
4
5
6
7
VCCQ
A6
A4
NC
A8
A16
VCCQ
NC
CE2
A3
ADV
A9
CE2
NC
NC
A7
A2
VCC
A12
A15
NC
DQc1
DQPc
GND
NC
GND
DQPb
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BWc
NC
BWb
DQb4
DQb3
DQc7
DQc8
GND
WE
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BWd
NC
BWa
DQa5
DQa6
VCCQ
DQd5
GND
CKE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
DQPd
GND
A0
GND
DQPa
DQa1
NC
A5
MODE
VCC
VCC
A13
NC
NC
NC
A10
A11
A14
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
119-pin PBGA (Top View) and 100-Pin TQFP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
VCC
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
VCC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
T
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
128K x 36
PIN DESCRIPTIONS
A0, A1
4
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
DQPa-DQPd
Parity Data I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
PIN CONFIGURATION
1
2
3
4
5
6
7
VCCQ
A6
A4
NC
A8
A16
VCCQ
NC
CE2
A3
ADV
A9
CE2
NC
NC
A7
A2
VCC
A12
A15
NC
DQ9
NC
GND
NC
GND
DQP1
NC
NC
DQ10
GND
CE
GND
NC
DQ8
VCCQ
NC
GND
OE
GND
DQ7
VCCQ
NC
DQ11
BWb
A17
NC
NC
DQ6
DQ12
NC
GND
WE
GND
DQ5
NC
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
NC
DQ13
GND
CLK
GND
NC
DQ4
DQ14
NC
NC
NC
BWa
DQ3
NC
VCCQ
DQ15
GND
CKE
GND
NC
VCCQ
DQ16
NC
GND
A1
GND
DQ2
NC
NC
DQP2
GND
A0
GND
NC
DQ1
NC
A5
MODE
VCC
VCC
A13
NC
NC
A10
A11
NC
A14
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A6
A7
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
119-pin PBGA (Top View) and 100-Pin TQFP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
VCC
VCC
VCC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
A10
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
VCC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A11
A12
A13
A14
A15
A16
A17
T
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
256K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
DQP1-DQP2
Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
5
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
STATE DIAGRAM
READ
READ
READ
BURST
WRITE
BEGIN
READ
DS
DS
READ
WRITE
DESELECT
BURST
BURST
READ
BEGIN
WRITE
WRITE
BURST
DS
BURST
DS
DS
WRITE
READ
WRITE
BURST
WRITE
BURST
SYNCHRONOUS TRUTH TABLE(1)
Operation
Not Selected Continue
Begin Burst Read
Continue Burst Read
NOP/Dummy Read
Dummy Read
Begin Burst Write
Continue Burst Write
NOP/Write Abort
Write Abort
Ignore Clock
Address
Used
CS1
CS2
CS2
ADV
WE
BWx
OE
CKE
CLK
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
X
L
X
L
X
L
X
L
X
X
X
H
X
H
X
H
X
H
X
X
X
L
X
L
X
L
X
L
X
X
H
L
H
L
H
L
H
L
H
X
X
H
X
H
X
L
X
L
X
X
X
X
X
X
X
L
L
H
H
X
X
L
L
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
ASYNCHRONOUS TRUTH TABLE(1)
Operation
ZZ
OE
I/O STATUS
Sleep Mode
H
L
L
L
L
X
L
H
X
X
High-Z
DQ
High-Z
Din, High-Z
High-Z
Read
Write
Deselected
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE,
otherwise data bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle
time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
WE
BWa
BWb
H
L
L
L
L
X
L
H
L
H
X
H
L
L
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x32/x36)
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
WE
BWa
BWb
BWc
BWd
H
L
L
L
L
L
L
X
L
H
H
H
L
H
X
H
L
H
H
L
H
X
H
H
L
H
L
H
X
H
H
H
L
L
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
7
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1) (MODE = GND)
Symbol
TBIAS
TSTG
PD
IOUT
VIN, VOUT
VIN
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
Value
Unit
–10 to +85
°C
–65 to +150
°C
1.6
W
100
mA
–0.5 to VCCQ + 0.3
V
–0.3 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
Industrial
VCC
3.3V ± 5%
3.3V ± 5%
3.3V ± 5%
-40°C to +85°C
VCCQ
3.3V ± 5%
2.5V ± 5%
3.3V ± 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
2.5V
3.3V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = 1.0 mA (2.5V)
2.0
—
2.4
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
Input HIGH Voltage
1.7
VCC + 0.3
2.0
VCC + 0.3
V
VIL
Input LOW Voltage
–0.3
0.7
–0.3
0.8
V
ILI
Input Leakage Current
GND ≤ VIN ≤ VCC
–5
5
–5
5
µA
ILO
Output Leakage Current
GND ≤ VOUT ≤ VCCQ, OE = VI
–5
5
–5
5
µA
Unit
(1)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-150*
MAX
x18 x32/36
-133
MAX
x18 x32/36
-100
MAX
x18 x32/36
Symbol
Parameter
Test Conditions
ICC
AC Operating
Supply Current
Device Selected,
Com.
OE = VIH, ZZ ≤ VIL,
IND.
All Inputs ≤ 0.2V OR ≥ VCC – 0.2V,
Cycle Time ≥ tKC min.
380
—
380
—
350
—
350
—
300
350
300
350
mA
ISB
Standby Current
TTL Input
Device Deselected,
COM.
VCC = Max.,
Ind.
All Inputs ≤ 0.2V OR ≥ VCC – 0.2V,
ZZ ≤ VIL, f = Max.
105
—
105
—
90
—
90
—
80
90
80
90
mA
ISBI
Standby Current
CMOS Input
Device Deselected,
Com.
VCC = Max.,
Ind.
VIN ≤ GND + 0.2V or ≥ VCC – 0.2V
f=0
20
—
20
—
20
—
20
—
20
25
20
25
mA
*This speed available only in NP version
Note:
1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits ±30 µA maximum leakage current when
tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
9
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
351 Ω
5 pF
Including
jig and
scope
1.5V
Figure 1
10
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
1,538 Ω
1.25V
Figure 3
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
5 pF
Including
jig and
scope
Figure 4
11
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-150*
Min. Max.
-133
Min. Max.
-100
Min. Max.
Symbol
Parameter
fmax
Clock Frequency
—
150
—
133
—
100
MHz
t KC
Cycle Time
6.7
—
7.5
—
10
—
ns
t KH
Clock High Time
2.5
—
3
—
3
—
ns
t KL
Clock Low Time
2.5
—
3
—
3
—
ns
tKQ
Clock Access Time
—
3.8
—
4.2
—
5
ns
tKQX(2)
Unit
Clock High to Output Invalid
1.5
—
1.5
—
1.5
—
ns
(2,3)
Clock High to Output Low-Z
0
—
0
—
0
—
ns
(2,3)
Clock High to Output High-Z
—
3
—
3.5
—
3.5
ns
Output Enable to Output Valid
—
3.8
—
4.2
—
5
ns
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
Output Disable to Output High-Z
—
3.5
—
3.5
—
3.5
ns
t AS
Address Setup Time
1.5
—
1.5
—
1.5
—
ns
tWS
Read/Write Setup Time
1.5
—
1.5
—
1.5
—
ns
t CES
Chip Enable Setup Time
1.5
—
1.5
—
1.5
—
ns
t SE
Clock Enable Setup Time
1.5
—
1.5
—
1.5
—
ns
tAVS
Address Advance Setup Time
1.5
—
1.5
—
1.5
—
ns
t DS
Data Setup Time
2.0
—
2.0
—
2.0
—
ns
t AH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
t HE
Clock EnableHold Time
0.5
—
0.5
—
0.5
—
ns
t WH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
t CEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
t ADVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
ns
t DH
Data Hold Time
0.5
—
0.5
—
0.5
—
ns
t PDS
ZZ High to Power Down
—
2
—
2
—
2
cyc
t PUS
ZZ Low to Power Down
—
2
—
2
—
2
cyc
tKQLZ
tKQHZ
tOEQ
tOELZ(2,3)
tOEHZ
(2,3)
*This speed available only in NP version
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
ISB2
Current during SLEEP MODE
t PDS
ZZ active to input ignored
2
cycle
t PUS
ZZ inactive to input sampled
2
cycle
tZZI
ZZ active to SLEEP current
2
cycle
tRZZI
ZZ inactive to exit SLEEP current
0
ns
ZZ ≥ Vih
Max.
Unit
10
mA
SLEEP MODE TIMING
K
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
13
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
READ CYCLE TIMING
tKH tKL
Clock
tKC
tADVS tADVH
ADV
tAS tAH
A16 - A0 or
A17 - A0
A1
A3
A2
tWS tWH
WE
tSE tHE
CKE
tCES tCEH
CE
OE
tOEQ
tOEHZ
tDS
tKQ
tKQHZ
tOEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
NOTES: WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
14
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
Don't Care
Undefined
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
WRITE CYCLE TIMING
tKH tKL
Clock
tKC
ADV
A16 - A0 or
A17 - A0
A1
A3
A2
WE
tSE tHE
CKE
CE
OE
tDS
Data In
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
tDH
D3-2
D3-3
D3-4
tOEHZ
Data Out
Q0-3
Q0-4
NOTES: WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
Don't Care
Undefined
15
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
SINGLE READ/WRITE CYCLE TIMING
tCH
tCL
Clock
tCES tCEH
tCYC
CKE
Address
A1
A2
A3
A4
Q1
Q3
A5
A6
A7
A8
A9
WRITE
CS
ADV
OE
tOE
tLZOE
Data Out
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
16
Q4
Q6
Q7
D5
Don't Care
Undefined
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
CKE OPERATION TIMING
tCH
tCL
Clock
tCES tCEH
tCYC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CS
ADV
OE
tCD
tHZC
tLZC
Data Out
Q1
Q3
Q4
tDS tDH
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
Don't Care
Undefined
17
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI
®
CS OPERATION TIMING
tCH
tCL
Clock
tCES tCEH
tCYC
CKE
Address
A1
A2
A3
A4
A5
WRITE
CS
ADV
OE
tOE
tCD
tHZC
tLZC
tLZOE
Data Out
Q1
Q2
Q4
tDS tDH
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
18
D5
Don't Care
Undefined
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency
Order Part Number
Package
128Kx32
ISSI
®
Industrial Range: -40°C to +85°C
Frequency
Order Part Number
Package
128Kx32
150
IS61NP12832-150TQ
IS61NP12832-150B
TQFP
PBGA
133
IS61NP12832-133TQ
IS61NP12832-133B
TQFP
PBGA
100
IS61NP12832-5TQ
IS61NP12832-5B
TQFP
PBGA
150
IS61NP12836-150TQ
IS61NP12836-150B
TQFP
PBGA
133
IS61NP12836-133TQ
IS61NP12836-133B
TQFP
PBGA
100
IS61NP12836-5TQ
IS61NP12836-5B
TQFP
PBGA
150
IS61NP25618-150TQ
IS61NP25618-150B
TQFP
PBGA
133
IS61NP25618-133TQ
IS61NP25618-133B
TQFP
PBGA
100
IS61NP25618-5TQ
IS61NP25618-5B
TQFP
PBGA
100
IS61NP12832-5TQI
TQFP
IS61NP12836-5TQI
TQFP
IS61NP25618-5TQI
TQFP
128Kx36
100
256Kx18
100
128Kx36
256Kx18
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
19
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency
Order Part Number
Package
128Kx32
ISSI
®
Industrial Range: -40°C to +85°C
Frequency
Order Part Number
Package
IS61NLP12832-5TQI
TQFP
IS61NLP12836-5TQI
TQFP
IS61NLP25618-5TQI
TQFP
128Kx32
133
IS61NLP12832-133TQ
IS61NLP12832-133B
TQFP
PBGA
100
IS61NLP12832-5TQ
IS61NLP12832-5B
TQFP
PBGA
100
128Kx36
100
256Kx18
128Kx36
133
IS61NLP12836-133TQ
IS61NLP12836-133B
TQFP
PBGA
100
IS61NLP12836-5TQ
IS61NLP12836-5B
TQFP
PBGA
133
IS61NLP25618-133TQ
IS61NLP25618-133B
TQFP
PBGA
100
IS61NLP25618-5TQ
IS61NLP25618-5B
TQFP
PBGA
100
256Kx18
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
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