ISSI IS61VVF409618B-7.5B2L 2m x 36, 4m x 18 72 mb synchronous flow-through static ram Datasheet

IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
2M x 36, 4M x 18
72 Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
ADVANCED INFORMATION
OCTOBER 2012
FEATURES
DESCRIPTION
• Internal self-timed write cycle
The 72Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and networking applications. The IS61LF/VF204836B is organized as
2,096,952 words by 36 bits. The IS61LF/VF409618B is
organized as 4,193,904 words by 18 bits. Fabricated with
ISSI's advanced CMOS technology, the device integrates
a 2-bit burst counter, high-speed SRAM core, and highdrive capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LF: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)
VF: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)
VVF: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165pin PBGA packages
• Lead-free available
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
tkq
tkc
Parameter
Clock Access Time
Cycle Time
Frequency
-6.5
6.5
7.5
133
-7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
1
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
BLOCK DIAGRAM
MODE
CLK
Q0
/CKE
BINARY
COUNTER
/ADV
/CE
/ADSC
/ADSP
/CLR
D
A0-x
x18: x=21
x36: x=20
Q1
A0
A1
A0`
A1`
2Mx36;
4Mx18
Memory Array
Q
ADDRESS
REGISTER
/CE
CLK
/GW
/BWE
/BW(a-x)
x18:x=b,
x32,x36:x=d
D
Q
DQ(a-d)
BYTE WRITE
REGISTERS
CLK
INPUT
REGISTER
/CE
CE2
D
/CE2
ENABLE
REGISTERS
ZZ
Power
Down
Q
CLK
OUTPUT
REGISTER
CLK
DQ(a-x)
x18:x=b,
x32,x36:x=d
CLK
/OE
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
165-PIN BGA
165-Ball, 13x15 mm BGA
165-Ball, 15x17 mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
119-PIN BGA
119-Ball, 14x22 mm BGA
1.27 mm Ball Pitch, 7 x 17 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
3
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
119 BGA PACKAGE PIN CONFIGURATION
2M x 36 (TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
VDDQ
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
2
A
A
A
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
A
TMS
3
A
A
A
Vss
Vss
Vss
4
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWc
Vss
NC
Vss
BWd
Vss
Vss
Vss
MODE
A
TDI
BWE
A1*
A0*
VDD
A
TCK
5
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
A
NC
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
4
Symbol
A
Pin Name
Synchronous Address Inputs
Symbol
OE
Pin Name
Asynchronous Output Enable
A0, A1
ADV
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
ZZ
Asynchronous Power Sleep Mode
MODE
ADSP
Synchronous Address Status Processor
Synchronous Burst Sequence Selection
TCK, TDO
JTAG Pins
ADSC
Synchronous Address Status Controller
GW
Synchronous Global Write Enable
CLK
CE
Synchronous Clock
Synchronous Chip Select
BWa-BWd
Synchronous Byte Write Controls
BWE
Synchronous Byte Write Enable
TMS, TDI
NC
No Connect
DQa-DQd
Synchronous Data Inputs/Outputs
DQPa-DQPd
Synchronous Parity Data Inputs/Outputs
Vdd
Power Supply
Vddq
I/O Power Supply
Vss
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
119 BGA PACKAGE PIN CONFIGURATION
4Mx18 (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQb
NC
VDDQ
NC
DQb
VDDQ
NC
DQb
VDDQ
DQb
NC
NC
A
VDDQ
2
A
A
A
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
A
TMS
3
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
MODE
A
TDI
4
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWE
A1*
A0*
VDD
NC
TCK
5
A
A
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
6
A
A
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
BWa
Vss
Vss
Vss
NC
A
TDO
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Synchronous Address Inputs
Symbol
OE
Pin Name
Asynchronous Output Enable
A0, A1
ADV
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
ZZ
Asynchronous Power Sleep Mode
MODE
Synchronous Burst Sequence Selection
ADSP
Synchronous Address Status Processor
TCK, TDO
JTAG Pins
ADSC
Synchronous Address Status Controller
TMS, TDI
GW
Synchronous Global Write Enable
NC
No Connect
CLK
CE
Synchronous Clock
Synchronous Chip Select
DQa-DQb
Synchronous Data Inputs/Outputs
Synchronous Byte Write Controls
DQPa-DQPb
BWa-BWb
Synchronous Parity Data Inputs/Outputs
BWE
Synchronous Byte Write Enable
Vdd
Power Supply
Vddq
I/O Power Supply
Vss
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
5
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
165 PBGA PACKAGE PIN CONFIGURATION
2M x 36 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWc
BWb
CE2
BWE
ADSC
ADV
A
NC
B
NC
A
CE2
BWd
BWa
CLK
GW
OE
ADSP
A
NC
C
DQPc
NC
Vddq
Vss
Vss
Vss
Vss
Vss
Vddq
NC
DQPb
D
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
E
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
F
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
G
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
H
NC
NC
NC
Vdd
Vss
Vss
Vss
Vdd
NC
NC
ZZ
J
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
K
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
L
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
M
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
N
DQPd
NC
Vddq
Vss
NC
A
NC
Vss
Vddq
NC
DQPa
P
NC
A
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
A
A
A
TMS
A0*
TCK
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
6
Symbol
A
Pin Name
Synchronous Address Inputs
Symbol
Pin Name
BWE
Synchronous Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep Mode
ADSP
Synchronous Address Status
Processor
MODE
Synchronous Burst Sequence Selection
JTAG Pins
ADSC
Synchronous Address Status
Controller
GW
Synchronous Global Write Enable
CLK
CE, CE2, CE2
Synchronous Clock
Synchronous Chip Select
BWa-BWd
Synchronous Byte Write Controls
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-DQPd
Vdd
Vddq
Vss
Ground
No Connect
Synchronous Data Inputs/Outputs
Synchronous Data Inputs/Outputs
Power Supply
I/O Power Supply
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
165 PBGA PACKAGE PIN CONFIGURATION
4M x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWb
NC
CE2
BWE
ADSC
ADV
A
A
B
NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP
A
NC
C
NC
NC
Vddq
Vss
Vss
Vss
Vss
Vss
Vddq
NC
DQPa
D
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
E
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
F
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
G
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
H
NC
NC
NC
Vdd
Vss
Vss
Vss
Vdd
NC
NC
ZZ
J
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
K
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
L
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
M
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
N
DQPb
NC
Vddq
Vss
NC
A
NC
Vss
Vddq
NC
NC
P
NC
A
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
A
A
A
TMS
A0*
TCK
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Synchronous Address Inputs
Symbol
BWE
Synchronous Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep Mode
ADSP
Synchronous Address Status Processor
MODE
Synchronous Burst Sequence Selection
ADSC
Synchronous Address Status Controller
JTAG Pins
GW
Synchronous Global Write Enable
CLK
CE, CE2, CE2
Synchronous Clock
Synchronous Chip Select
BWa-BWb
Synchronous Byte Write Controls
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-DQPb
Vdd
Vddq
Vss
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
Pin Name
No Connect
Synchronous Data Inputs/Outputs
Synchronous Data Inputs/Outputs
Power Supply
I/O Power Supply
7
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
PIN CONFIGURATION
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-PIN TQFP (2M X 36)
DQPc
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable option)
PIN DESCRIPTIONS
A0, A1
A
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
8
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Synchronous Parity Data Input/Output
GW
Synchronous Global Write Enable
MODE Synchronous Burst Sequence Mode
Selection
OE
Asynchronous Output Enable
Vdd
Power Supply
Vddq
Vss
ZZ
I/O Power Supply
Ground
Asynchronous Snooze Enable
Synchronous Clock
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
PIN CONFIGURATION
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-PIN TQFP (4M X 18)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
(3 Chip-Enable Option)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQb
Synchronous Data Input/Output
DQPa-DQPb
Synchronous Parity Data Input/Output
GW
MODE Synchronous Global Write Enable
Synchronous Burst Sequence Mode
Selection
OE
Vdd
Vddq
Vss
ZZ
Asynchronous Output Enable
Power Supply
I/O Power Supply
Ground
Asynchronous Snooze Enable
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
9
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
TRUTH TABLE(1-8)
OPERATION
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
ADDRESS CE
None
H
None
L
None
L
None
L
None
L
None
X
External
L
External
L
External
L
External
L
External
L
Next
X
Next
X
Next
H
Next
H
Next
X
Next
H
Current
X
Current
X
Current
H
Current
H
Current
X
Current
H
CE2
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ ADSP ADSC ADV WRITE OE
L
X
L
X
X
X
L
L
X
X
X
X
L
L
X
X
X
X
L
H
L
X
X
X
L
H
L
X
X
X
H
X
X
X
X
X
L
L
X
X
X
L
L
L
X
X
X
H
L
H
L
X
L
X
L
H
L
X
H
L
L
H
L
X
H
H
L
H
H
L
H
L
L
H
H
L
H
H
L
X
H
L
H
L
L
X
H
L
H
H
L
H
H
L
L
X
L
X
H
L
L
X
L
H
H
H
H
L
L
H
H
H
H
H
L
X
H
H
H
L
L
X
H
H
H
H
L
H
H
H
L
X
L
X
H
H
L
X
CLK
DQ
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
X
High-Z
L-H
Q
L-H High-Z
L-H
D
L-HQ
L-H High-Z
L-H
Q
L-H High-Z
L-H
Q
L-H High-Z
L-H
D
L-H
D
L-H
Q
L-H High-Z
L-H
Q
L-H High-Z
L-H
D
L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
10
GW
H
H
H
H
L
BWE
H
L
L
L
X
BWa
X
H
L
L
X
BWb
X
H
H
L
X
BWc
X
H
H
L
X
BWd
X
H
H
L
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
POWER UP SEQUENCE
Vddq → Vdd1 → I/O Pins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the
same time as Vddq provided Vih (level of I/O pins) is lower than Vddq.
POWER-UP INITIALIZATION TIMING
VDD
power > 1ms
VDD
VDDQ
Device Initialization
Device ready for
normal operation
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
11
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Tstg
Pd
Iout
Vin, Vout
Vin
Vdd
Parameter
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to Vss for I/O Pins
Voltage Relative to Vss for
for Address and Control Inputs
Voltage on Vdd Supply Relative to Vss
LF Value
–55 to +150
1.6
100
–0.5 to Vddq + 0.5
–0.5 to Vdd + 0.5
VF/VVF Value
–55 to +150
1.6
100
–0.5 to Vddq + 0.3
–0.5 to Vdd + 0.3
Unit
°C
W
mA
V
V
–0.5 to Vdd + 0.5
–0.3 to Vdd + 0.3
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61LFxxxxx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
Vdd
3.3V ± 5%
3.3V ± 5%
Vddq
3.3V/2.5V ± 5%
3.3V/2.5V ± 5%
Vdd
2.5V ± 5%
2.5V ± 5%
Vddq
2.5V ± 5%
2.5V ± 5%
Vdd
1.8V ± 5%
1.8V ± 5%
Vddq
1.8V ± 5%
1.8V ± 5%
OPERATING RANGE (IS61VFxxxxx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
OPERATING RANGE (IS61VVFxxxxx)
Range
Commercial
Industrial
12
Ambient Temperature
0°C to +70°C
-40°C to +85°C
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 1, 2, 3
3.3V2.5V1.8V
Symbol Parameter
Test Conditions
Min.Max.
Min. Max.
Min.Max.
Unit
Voh
Output HIGH Voltage
Ioh = –4.0 mA (3.3V)
2.4 —
2.0 —
Vddq - 0.4 —
V
Ioh = –1.0 mA (2.5V, 1.8V)
Vol
Output LOW Voltage
Iol = 8.0 mA (3.3V)
— 0.4
— 0.4
— 0.4
V
Iol = 1.0 mA (2.5V, 1.8V)
Vih
Input HIGH Voltage 2.0Vdd + 0.3
1.7
Vdd + 0.3
0.6VddVdd + 0.3
V
Vil
Input LOW Voltage
–0.3 0.8
–0.3 0.7
–0.3 0.3Vdd
V
(1,4)
Ili
Input Leakage Current
Vss ≤ Vin ≤ Vdd
–55
–55
–55
µA
Input Current of MODE
Vss ≤ Vin ≤ Vdd(5)
–30 5
–30 5
–30 5
Input Current of ZZ
Vss ≤ Vin ≤ Vdd(6)
–5 30
–5 30
–5 30
Ilo
Output Leakage Current Vss ≤ Vout ≤ Vddq, OE = Vih –55
–5 5
–55
µA
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
4. Except MODE and ZZ
5. MODE is connected to pull-up resister internally.
6. ZZ is connected to pull-down resister internally.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Icc
AC Operating
Supply Current
Isb
Standby Current
TTL Input
Isbi
Standby Current
CMOS Input
Test Conditions
Temp. range
Device Selected,
Com.
OE = Vih, ZZ ≤ Vil,
Ind.
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V,
Cycle Time ≥ tkc min.
Device Deselected,
Com.
Vdd = Max.,
Ind.
All Inputs ≤ Vil or ≥ Vih,
ZZ ≤ Vil, f = Max.
Device Deselected,
Com.
Vdd = Max.,
Ind.
Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V
f=0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
6.5
7.5
MAX
MAX
x18
x36
x18
x36
260 260
240 240
270 270 250 250
Unit
mA
130
135
130
135
130
135
130
135
mA
115
120
115
120
115
120
115
120
mA
13
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
OUTPUT
50Ω
1.5V
Figure 1
14
OUTPUT
5 pF
Including
jig and
scope
351 Ω
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
1.8V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 1.8V
1.5 ns
0.9V
See Figures 5 and 6
1.8V I/O OUTPUT LOAD EQUIVALENT
1K Ω
+1.8V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1K Ω
0.9V
Figure 5
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
Figure 6
15
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
fmax
tkc
tkh
tkl
tkq
tkqx(2)
tkqlz(2,3)
tkqhz(2,3)
toeq
toelz(2,3)
toehz(2,3)
tas
tss
tws
tces
tavs
tds
tah
tsh
twh
tceh
tavh
tdh
tpower(4)
Notes:
1.
2.
3.
4.
16
Parameter
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Address Status Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Data Setup Time
Address Hold Time
Address Status Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
Vdd (typical) to First Access
6.5
Min.
—
7.5
2.2
2.2
—
2.5
2.5
—
—
0
—
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
Max.
133
—
—
—
6.5
—
—
3.8
3.2
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
7.5
Min. Max.
—
117
8.5
—
2.5
—
2.5
—
—
7.5
2.5
—
2.5
—
—
4.0
—
3.4
0
—
—
3.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Configuration signal MODE is static and must not change during normal operation.
Guaranteed but not 100% tested. This parameter is periodically sampled.
Tested with load in Figure 2.
tpower is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be
initiated.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC
ADV
tAS
Address
tAH
RD1
WR1
tWS
tWH
tWS
tWH
RD2
RD3
GW
BWE
tWS
tWH
WR1
BWd-BWa
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
CE2 and CE2 only sampled with ADSP or ADSC
CE2
Unselected with CE2
CE2
tOELZ
tOEHZ
tOEQ
OE
tKQX
DATAOUT
High-Z
High-Z
tKQLZ
tKQ
1a
tKQLZ
tKQ
DATAIN
2a
2c
2d
tKQHZ
tKQX
1a
High-Z
tDS
Single Read
Flow-through
tDH
Single Write
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
2b
Burst Read
Unselected
17
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE1 inactive
ADSP
ADSC initiate Write
ADSC
ADV must be inactive for ADSP Write tAVS
tAVH
ADV
tAS
Address
tAH
WR1
WR2
tWS
tWH
tWS
tWH
tWS
tWH
WR3
GW
BWE
BWd-BWa
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE1 Masks ADSP
CE
Unselected with CE2
CE2 and CE3 only sampled with ADSP or ADSC
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
18
tDH
1a
BW4-BW1 only are applied to first cycle of WR2
2a
2b
2c
2d
Burst Write
3a
Write
Unselected
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions
Temp. Range
Isb2
Current during SNOOZE MODE
ZZ ≥ Vdd - 0.2V
Com.
Ind.
Auto.
tpds
ZZ active to input ignored
tpus
ZZ inactive to input sampled
tzzi
ZZ active to SNOOZE current
trzzi
ZZ inactive to exit SNOOZE current
Min.
—
—
—
—
2
—
0
Max.
Unit
80
mA
90
100
2
cycle
—
cycle
2
cycle
—
ns
SNOOZE MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
19
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
The serial boundary scan Test Access Port (TAP) is only
available in the PBGA package. This port operates in accordance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices
using 1149.1 fully compliant TAPs.
The test clock is only used with the TAP controller. All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
DISABLING THE JTAG FEATURE
TEST DATA-IN (TDI)
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to Vdd through a pull-up resistor.
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
The TDI pin is used to serially input information to the
registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB)
on any register.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
31 30 29
. . .
Selection Circuitry
2
1
0
2
1
0
TDO
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
20
TAP CONTROLLER
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller
State Diagram). The output changes on the falling edge
of TCK and TDO is connected to the Least Significant Bit
(LSB) of any register.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (Vdd) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
ister is set LOW (Vss) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Instruction Register
Register Name
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass reg-
Scan Register Sizes
Instruction
Bypass
ID
Boundary Scan
Bit Size
(x18)
3
1
32
75
Bit Size
(x36)
3
1
32
75
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Description
Reserved for version number.
Defines depth of SRAM. 2M or 4M
Defines with of the SRAM. x36 or x18
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
2M x 36
xxxx
01010
00100
xxxxx
00001010101
1
4M x 18
xxxx
01011
00011
xxxxx
00001010101
1
21
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
TAP INSTRUCTION SET
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM
is not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; instead it performs a capture of the Inputs and
Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted from
the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant. When the
SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock
runs more than an order of magnitude faster. Because of
the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition (metastable state). The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up
plus hold times (tcs and tch). To insure that the SRAM clock
input is captured correctly, designs need a way to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction.
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK and CLK
captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When an
EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST
places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also places
all SRAM outputs into a High-Z state.
22
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state,
the bypass register is placed between the TDI and TDO
pins. The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
INSTRUCTION CODES
Code
000
Instruction
EXTEST
001
IDCODE
010
SAMPLE-Z
011
100
RESERVED
SAMPLE/PRELOAD
101
RESERVED
110
111
RESERVED
BYPASS
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
Run Test/Idle
1
Select DR
0
0
1
1
1
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
Exit1 IR
0
Pause DR
0
1
0
1
Exit2 DR
1
Update DR
0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
Capture IR
0
Shift IR
1
0
Pause IR
1
0
1
1
0
1
0
Exit2 IR
1
Update IR
0
23
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
TAP Electrical Characteristics (Vddq = 3.3V Operating Range)
Symbol
Voh1
Voh2
Vol1
Vol2
Vih
Vil
Ix
Parameter
Test Conditions
Min.
Max.
Output HIGH Voltage
Ioh = -4 mA
2.4
—
Output HIGH Voltage
Ioh = -100 µA
2.9
—
Output LOW Voltage
Iol = 8 mA
—
0.4
Output LOW Voltage
Iol = 100 µA
—
0.2
Input HIGH Voltage
2.0
Vdd+0.3
Input LOW Voltage
–0.3
0.8
Input Load Current
Vss ≤ Vin ≤ Vddq
–30
30
Units
V
V
V
V
V
V
mA
TAP Electrical Characteristics (Vddq = 2.5V Operating Range)
Symbol
Voh1
Parameter
Output HIGH Voltage
Test Conditions
Ioh = -1 mA
Min.
2.0
Max.
—
Voh2
Vol1
Vol2
Vih
Vil
Ix
Output HIGH Voltage
Ioh = -100 µA
2.1
—
Output LOW Voltage
Iol = 1 mA
—
0.4
Output LOW Voltage
Iol = 100 µA
—
0.2
Input HIGH Voltage
1.7
Vdd+0.3
Input LOW Voltage
-0.3
0.7
Input Load Current
Vss ≤ Vin ≤ Vddq
–30
30
Units
V
V
V
V
V
V
mA
TAP Electrical Characteristics (Vddq = 1.8V Operating Range)
Symbol
Voh1
Vol1
Vih
Vil
Ix
24
Parameter
Test Conditions
Min.
Max.
Output HIGH Voltage
Ioh = -1.0 mA
Vdd -0.4
—
Output LOW Voltage
Iol = 1.0 mA
—
0.5
Input HIGH Voltage
1.3
Vdd +0.3
Input LOW Voltage
-0.3
0.7
Input Load Current
Vss ≤ V I ≤ Vddq
-30
30
Units
V
V
V
V
mA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
TAP AC ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGE)
Parameter
Symbol
Min
Max
Units
TCK cycle time
tTHTH
100
–
ns
TCK high pulse width
tTHTL
40
–
ns
TCK low pulse width
tTLTH
40
–
ns
TMS Setup
tMVTH
10
–
ns
TMS Hold
tTHMX
10
–
ns
TDI Setup
tDVTH
10
–
ns
TDI Hold
tTHDX
10
–
ns
TCK Low to Valid Data
tTLOV
–
20
ns
TAP Output Load Equivalent
TAP AC TEST CONDITIONS (1.8V/2.5V/3.3V)
Input pulse levels
0 to 1.8V/0 to 2.5V/0 to 3.0V
Input rise and fall times
1.5ns
Input timing reference levels
0.9V/1.25V/1.5V
Output reference levels
0.9V/1.25V/1.5V
Test load termination supply voltage
0.9V/1.25V/1.5V
50Ω
1.25V/1.5V
TDO
Z0 = 50Ω
20 pF
GND
TAP TIMING
1
2
tTHTH
3
4
5
6
tTLTH
TCK
tTHTL
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLOV
TDO
tTLOX
DON'T CARE
UNDEFINED
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
25
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
BOUNDARY SCAN ORDER
165 BGA
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
X36
Bump ID
Signal
N6
A9
N7
NC
N10
NC
P11
A8
P8
A18
R8
A17
R9
A16
P9
A15
P10
A14
R10
A13
R11
A12
H11
ZZ
N11
DQa0
M11
DQa1
L11
DQa2
K11
DQa6
J11
DQa7
M10
DQa3
L10
DQa4
K10
DQa5
J10
DQa8
H9
NC
H10
NC
G11
DQb8
F11
DQb7
E11
DQb5
D11
DQb4
G10
DQb6
F10
DQb3
E10
DQb2
D10
DQb1
C11
DQb0
A11
NC
B11
NC
A10
A11
B10
A10
A9
/ADV
B9
/ADSP
C10
NC
A8
/ADSC
B8
/OE
A7
/BWE
B7
/GW
B6
CLK
X18
Bump ID
Signal
N6
A9
N7
NC
N10
NC
P11
A8
P8
A18
R8
A17
R9
A16
P9
A15
P10
A14
R10
A13
R11
A12
H11
ZZ
N11
NC
M11
NC
L11
NC
K11
NC
J11
NC
M10
DQa8
L10
DQa7
K10
DQa6
J10
DQa5
H9
NC
H10
NC
G11
DQa4
F11
DQa3
E11
DQa2
D11
DQa1
G10
NC
F10
NC
E10
NC
D10
NC
C11
DQa0
A11
A21
B11
NC
A10
A11
B10
A10
A9
/ADV
B9
/ADSP
C10
NC
A8
/ADSC
B8
/OE
A7
/BWE
B7
/GW
B6
CLK
119 BGA
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
X36
Bump ID
Signal
NC
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
T7
ZZ
P6
DQa0
N7
DQa1
M6
DQa2
L7
DQa6
K6
DQa7
P7
DQa3
N6
DQa4
L6
DQa5
K7
DQa8
NC
NC
H6
DQb8
G7
DQb7
F6
DQb5
E7
DQb4
H7
DQb6
G6
DQb3
E6
DQb2
D7
DQb1
D6
DQb0
T1
NC
NC
A11
A10
G4
/ADV
A4
/ADSP
NC
B4
/ADSC
F4
/OE
M4
/BWE
H4
/GW
K4
CLK
X18
Bump ID
Signal
NC
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
T7
ZZ
P6
NC
N7
NC
M6
NC
L7
NC
K6
NC
P7
DQa8
N6
DQa7
L6
DQa6
K7
DQa5
NC
NC
H6
DQa4
G7
DQa3
F6
DQa2
E7
DQa1
H7
NC
G6
NC
E6
NC
D7
NC
D6
DQa0
T1
A21
NC
A11
A10
G4
/ADV
A4
/ADSP
NC
B4
/ADSC
F4
/OE
M4
/BWE
H4
/GW
K4
CLK
Continued on next page
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
165 BGA
X36
X18
Bump ID
Signal
Bump ID
Signal
A6
/CE2
A6
/CE2
B5
/Bwa
B5
/Bwa
A5
/Bwb
A5
NC
A4
/Bwc
A4
/Bwb
B4
/Bwd
B4
NC
B3
CE2
B3
CE2
A3
/CE1
A3
/CE1
A2
A7
A2
A7
B2
A6
B2
A6
C2
NC
C2
NC
B1
NC
B1
NC
A1
NC
A1
NC
C1
DQc0
C1
NC
D1
DQc1
D1
NC
E1
DQc2
E1
NC
F1
DQc6
F1
NC
G1
DQc7
G1
NC
D2
DQc3
D2
DQb8
E2
DQc4
E2
DQb7
F2
DQc5
F2
DQb6
G2
DQc8
G2
DQb5
H1
NC
H1
NC
H2
NC
H2
NC
H3
NC
H3
NC
J1
DQd8
J1
DQb4
K1
DQd7
K1
DQb3
L1
DQd5
L1
DQb2
M1
DQd4
M1
DQb1
J2
DQd6
J2
NC
K2
DQd3
K2
NC
L2
DQd2
L2
NC
M2
DQd1
M2
NC
N1
DQd0
N1
DQb0
N2
NC
N2
NC
P1
NC
P1
NC
R1
MODE
R1
MODE
R2
A4
R2
A4
P3
A3
P3
A3
R3
A2
R3
A2
P2
A5
P2
A5
R4
A19
R4
A19
P4
A20
P4
A20
N5
NC
N5
NC
P6
A1
P6
A1
R6
A0
R6
A0
*
Int
*
Int
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
119 BGA
X36
X18
Bump ID
Signal
Bump ID
Signal
B6
A9
B6
A9
L5
/Bwa
L5
/Bwa
G5
/Bwb
G5
NC
G3
/Bwc
G3
/Bwb
L3
/Bwd
L3
NC
B2
A8
B2
A8
E4
/CE1
E4
/CE1
A7
A7
A6
A6
NC
NC
NC
NC
NC
NC
D2
DQc0
D2
NC
E1
DQc1
E1
NC
F2
DQc2
F2
NC
G1
DQc6
G1
NC
H2
DQc7
H2
NC
D1
DQc3
D1
DQb8
E2
DQc4
E2
DQb7
G2
DQc5
G2
DQb6
H1
DQc8
H1
DQb5
NC
NC
NC
NC
NC
NC
K2
DQd8
K2
DQb4
L1
DQd7
L1
DQb3
M2
DQd5
M2
DQb2
N1
DQd4
N1
DQb1
K1
DQd6
K1
NC
L2
DQd3
L2
NC
N2
DQd2
N2
NC
P1
DQd1
P1
NC
P2
DQd0
P2
DQb0
NC
NC
NC
NC
R3
MODE
R3
MODE
A4
A4
A3
A3
A2
A2
A5
A5
A19
A19
T2
A20
T2
A20
NC
NC
N4
A1
N4
A1
P4
A0
P4
A0
*
Int
*
Int
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
27
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
ORDERING INFORMATION
Commercial Range: 0°C to 70°C(VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time
6.5ns
7.5ns
x36
x18
Package
IS61LF204836B-6.5TQ
IS61LF409618B-6.5TQ
100 TQFP
IS61LF204836B-6.5B3
IS61LF409618B-6.5B3
165 PBGA,13x15mm
IS61LF204836B-6.5M3
IS61LF409618B-6.5M3
165 PBGA,15x17mm
IS61LF204836B-6.5B2
IS61LF409618B-6.5B2
119 PBGA
IS61LF204836B-6.5TQL
IS61LF409618B-6.5TQL
100 TQFP, Lead-free
IS61LF204836B-6.5B3L
IS61LF409618B-6.5B3L
165 PBGA,13x15mm, Lead-free
IS61LF204836B-6.5M3L
IS61LF409618B-6.5M3L
165 PBGA,15x17mm, Lead-free
IS61LF204836B-6.5B2L
IS61LF409618B-6.5B2L
119 PBGA, Lead-free
IS61LF204836B-7.5TQ
IS61LF409618B-7.5TQ
100 TQFP
IS61LF204836B-7.5B3
IS61LF409618B-7.5B3
165 PBGA,13x15mm
IS61LF204836B-7.5M3
IS61LF409618B-7.5M3
165 PBGA,15x17mm
IS61LF204836B-7.5B2
IS61LF409618B-7.5B2
119 PBGA
IS61LF204836B-7.5TQL
IS61LF409618B-7.5TQL
100 TQFP, Lead-free
IS61LF204836B-7.5B3L
IS61LF409618B-7.5B3L
165 PBGA,13x15mm, Lead-free
IS61LF204836B-7.5M3L
IS61LF409618B-7.5M3L
165 PBGA,15x17mm, Lead-free
IS61LF204836B-7.5B2L
IS61LF409618B-7.5B2L
119 PBGA, Lead-free
Commercial Range: 0°C to 70°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time x36
6.5ns
7.5ns
28
x18
Package
IS61VF204836B-6.5TQ
IS61VF409618B-6.5TQ
100 TQFP
IS61VF204836B-6.5B3
IS61VF409618B-6.5B3
165 PBGA,13x15mm
IS61VF204836B-6.5M3
IS61VF409618B-6.5M3
165 PBGA,15x17mm
IS61VF204836B-6.5B2
IS61VF409618B-6.5B2
119 PBGA
IS61VF204836B-6.5TQL
IS61VF409618B-6.5TQL
100 TQFP, Lead-free
IS61VF204836B-6.5B3L
IS61VF409618B-6.5B3L
165 PBGA,13x15mm, Lead-free
IS61VF204836B-6.5M3L
IS61VF409618B-6.5M3L
165 PBGA,15x17mm, Lead-free
IS61VF204836B-6.5B2L
IS61VF409618B-6.5B2L
119 PBGA, Lead-free
IS61VF204836B-7.5TQ
IS61VF409618B-7.5TQ
100 TQFP
IS61VF204836B-7.5B3
IS61VF409618B-7.5B3
165 PBGA,13x15mm
IS61VF204836B-7.5M3
IS61VF409618B-7.5M3
165 PBGA,15x17mm
IS61VF204836B-7.5B2
IS61VF409618B-7.5B2
119 PBGA
IS61VF204836B-7.5TQL
IS61VF409618B-7.5TQL
100 TQFP, Lead-free
IS61VF204836B-7.5B3L
IS61VF409618B-7.5B3L
165 PBGA,13x15mm, Lead-free
IS61VF204836B-7.5M3L
IS61VF409618B-7.5M3L
165 PBGA,15x17mm, Lead-free
IS61VF204836B-7.5B2L
IS61VF409618B-7.5B2L
119 PBGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
Commercial Range: 0°C to 70°C(VDD = 1.8V / VDDQ = 1.8V)
Access Time
7.5ns
x36
x18
Package
IS61VVF204836B-7.5TQ
IS61VVF409618B-7.5TQ
100 TQFP
IS61VVF204836B-7.5B3
IS61VVF409618B-7.5B3
165 PBGA,13x15mm
IS61VVF204836B-7.5M3
IS61VVF409618B-7.5M3
165 PBGA,15x17mm
IS61VVF204836B-7.5B2
IS61VVF409618B-7.5B2
119 PBGA
IS61VVF204836B-7.5TQL
IS61VVF409618B-7.5TQL
100 TQFP, Lead-free
IS61VVF204836B-7.5B3L
IS61VVF409618B-7.5B3L
165 PBGA,13x15mm, Lead-free
IS61VVF204836B-7.5M3L
IS61VVF409618B-7.5M3L
165 PBGA,15x17mm, Lead-free
IS61VVF204836B-7.5B2L
IS61VVF409618B-7.5B2L
119 PBGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time
6.5ns
7.5ns
x36
x18
Package
IS61LF204836B-6.5TQI
IS61LF409618B-6.5TQI
100 TQFP
IS61LF204836B-6.5B3I
IS61LF409618B-6.5B3I
165 PBGA,13x15mm
IS61LF204836B-6.5M3I
IS61LF409618B-6.5M3I
165 PBGA,15x17mm
IS61LF204836B-6.5B2I
IS61LF409618B-6.5B2I
119 PBGA
IS61LF204836B-6.5TQLI
IS61LF409618B-6.5TQLI
100 TQFP, Lead-free
IS61LF204836B-6.5B3LI
IS61LF409618B-6.5B3LI
165 PBGA,13x15mm, Lead-free
IS61LF204836B-6.5M3LI
IS61LF409618B-6.5M3LI
165 PBGA,15x17mm, Lead-free
IS61LF204836B-6.5B2LI
IS61LF409618B-6.5B2LI
119 PBGA, Lead-free
IS61LF204836B-7.5TQI
IS61LF409618B-7.5TQI
100 TQFP
IS61LF204836B-7.5B3I
IS61LF409618B-7.5B3I
165 PBGA,13x15mm
IS61LF204836B-7.5M3I
IS61LF409618B-7.5M3I
165 PBGA,15x17mm
IS61LF204836B-7.5B2I
IS61LF409618B-7.5B2I
119 PBGA
IS61LF204836B-7.5TQLI
IS61LF409618B-7.5TQLI
100 TQFP, Lead-free
IS61LF204836B-7.5B3LI
IS61LF409618B-7.5B3LI
165 PBGA,13x15mm, Lead-free
IS61LF204836B-7.5M3LI
IS61LF409618B-7.5M3LI
165 PBGA,15x17mm, Lead-free
IS61LF204836B-7.5B2LI
IS61LF409618B-7.5B2LI
119 PBGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
29
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
Industrial Range: -40°C to +85°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time
6.5ns
7.5ns
x36
x18
Package
IS61VF204836B-6.5TQI
IS61VF409618B-6.5TQI
100 TQFP
IS61VF204836B-6.5B3I
IS61VF409618B-6.5B3I
165 PBGA,13x15mm
IS61VF204836B-6.5M3I
IS61VF409618B-6.5M3I
165 PBGA,15x17mm
IS61VF204836B-6.5B2I
IS61VF409618B-6.5B2I
119 PBGA
IS61VF204836B-6.5TQLI
IS61VF409618B-6.5TQLI
100 TQFP, Lead-free
IS61VF204836B-6.5B3LI
IS61VF409618B-6.5B3LI
165 PBGA,13x15mm, Lead-free
IS61VF204836B-6.5M3LI
IS61VF409618B-6.5M3LI
165 PBGA,15x17mm, Lead-free
IS61VF204836B-6.5B2LI
IS61VF409618B-6.5B2LI
119 PBGA, Lead-free
IS61VF204836B-7.5TQI
IS61VF409618B-7.5TQI
100 TQFP
IS61VF204836B-7.5B3I
IS61VF409618B-7.5B3I
165 PBGA,13x15mm
IS61VF204836B-7.5M3I
IS61VF409618B-7.5M3I
165 PBGA,15x17mm
IS61VF204836B-7.5B2I
IS61VF409618B-7.5B2I
119 PBGA
IS61VF204836B-7.5TQLI
IS61VF409618B-7.5TQLI
100 TQFP, Lead-free
IS61VF204836B-7.5B3LI
IS61VF409618B-7.5B3LI
165 PBGA,13x15mm, Lead-free
IS61VF204836B-7.5M3LI
IS61VF409618B-7.5M3LI
165 PBGA,15x17mm, Lead-free
IS61VF204836B-7.5B2LI
IS61VF409618B-7.5B2LI
119 PBGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 1.8V / VDDQ = 1.8V)
Access Time
7.5ns
x36
x18
Package
IS61VVF204836B-7.5TQI
IS61VVF409618B-7.5TQI
100 TQFP
IS61VVF204836B-7.5B3I
IS61VVF409618B-7.5B3I
165 PBGA,13x15mm
IS61VVF204836B-7.5M3I
IS61VVF409618B-7.5M3I
165 PBGA,15x17mm
IS61VVF204836B-7.5B2I
IS61VVF409618B-7.5B2I
119 PBGA
IS61VVF204836B-7.5TQLI
IS61VVF409618B-7.5TQLI
100 TQFP, Lead-free
IS61VVF204836B-7.5B3LI
IS61VVF409618B-7.5B3LI
165 PBGA,13x15mm, Lead-free
IS61VVF204836B-7.5M3LI
IS61VVF409618B-7.5M3LI
165 PBGA,15x17mm, Lead-free
IS61VVF204836B-7.5B2LI
IS61VVF409618B-7.5B2LI
119 PBGA, Lead-free
Automotive(A3) Range: -40°C to +125°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time
x36
x18
Package
Please contact ISSI [email protected]
Automotive(A3) Range: -40°C to +125°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time x36
x18
Package
Please contact ISSI [email protected]
Automotive(A3) Range: -40°C to +125°C (VDD = 1.8V / VDDQ = 1.8V)
Access Time x36
x18
Package
Please contact ISSI [email protected]
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
31
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
Package Outline
1. CONTROLLING DIMENSION : MM .
NOTE :
08/28/2008
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
33
34
Package Outline
1. Controlling dimension : mm
NOTE :
12/10/2007
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
10/15/2012
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