ISSI IS61WV10248BLL-10TI 1m x 8 high-speed cmos static ram Datasheet

IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
1M x 8 HIGH-SPEED CMOS STATIC RAM
JUNE 2008
FEATURES
DESCRIPTION
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single power supply
– VDD 1.65V to 2.2V (IS61WV10248ALL)
speed = 20ns for Vcc = 1.65V to 2.2V
– VDD 2.4V to 3.6V (IS61/64WV10248BLL)
speed = 10ns for Vcc = 2.4V to 3.6V
speed = 8ns for Vcc = 3.3V + 5%
• Packages available:
– 48-ball miniBGA (9mm x 11mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
The ISSI IS61WV10248ALL/BLL and IS64WV10248BLL
are very high-speed, low power, 1M-word by 8-bit CMOS
static RAM. The IS61WV10248ALL/BLL and
IS64WV10248BLL are fabricated using ISSI's highperformance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
The IS61WV10248ALL/BLL and IS64WV10248BLL
operate from a single power supply and all inputs are
TTL-compatible.
The IS61WV10248ALL/BLL and IS64WV10248BLL are
available in 48 ball mini BGA and 44-pin TSOP (Type II)
packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A19
DECODER
1M X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CE
OE
CONTROL
CIRCUIT
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
1
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
PIN CONFIGURATION
48-pin Mini BGA (M ) (9mm x 11mm)
1
2
3
4
5
44-pin TSOP (Type II )
6
A
NC
OE
A0
A1
A2
NC
B
NC
NC
A3
A4
CE
I/O0
C
NC
NC
A5
A6
I/O1
I/O2
D
GND
NC
A17
A7
I/O3
VDD
E
VDD
NC
NC
A16
I/O4
GND
F
NC
NC
A14
A15
I/O5
I/O6
G
NC
NC
A12
A13
WE
I/O7
H
A18
A8
A9
A10
A11
A19
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
A19
NC
NC
PIN DESCRIPTIONS
2
A0-A19
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Data Input / Output
VDD
Power
GND
Ground
NC
No Connection
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
TRUTH TABLE
Mode
WE
Not Selected
(Power-down)
Output Disabled
Read
Write
CE
OE
I/O Operation
VDD Current
X
H
X
High-Z
ISB1, ISB2
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VDD
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
VDD Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to VDD + 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
3
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
OPERATING RANGE (VDD) (IS61WV10248ALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
VDD (20 nS)
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
OPERATING RANGE (VDD) (IS61WV10248BLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
VDD (8 nS)
3.3V + 5%
3.3V + 5%
VDD (10 nS)
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of
3.3V + 5%, the device meets 8ns.
OPERATING RANGE (VDD) (IS64WV10248BLL)
Range
Automotive
4
Ambient Temperature
–40°C to +125°C
VDD (10 nS)
2.4V-3.6V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage(1)
2
VDD + 0.3
V
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
µA
Min.
Max.
Unit
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width ≤ 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
VDD = Min., IOH = –1.0 mA
1.8
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 1.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VDD + 0.3
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width ≤ 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol
Parameter
Test Conditions
VDD
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.65-2.2V
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
1.65-2.2V
—
0.2
V
VIH
Input HIGH Voltage
1.65-2.2V
1.4
VDD + 0.2
V
VIL(1)
Input LOW Voltage
1.65-2.2V
–0.2
0.4
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width ≤ 10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
5
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
AC TEST CONDITIONS (HIGH SPEED)
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
(2.4V-3.6V)
0.4V to VDD-0.3V
1.5ns
VDD/2
Unit
(3.3V + 5%)
0.4V to VDD-0.3V
1.5ns
VDD/2 + 0.05
Unit
(1.65V-2.2V)
0.4V to VDD-0.2V
1.5ns
VDD/2
See Figures 1 and 2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
ZO = 50Ω
3.3V
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
6
5 pF
Including
jig and
scope
353 Ω
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol Parameter
Test Conditions
ICC
VDD = Max.,
IOUT = 0 mA, f = fMAX
ICC1
VDD Dynamic Operating
Supply Current
Min.
Max.
Com.
Ind.
Auto.
typ.(2)
—
—
—
110
120
—
-10
Min. Max.
—
—
—
-20
Min. Max.
Unit
95
100
140
—
—
—
90
100
140
mA
60
Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
30
35
—
—
—
—
30
35
60
—
—
—
30
35
70
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
30
35
—
—
—
—
30
35
70
—
—
—
30
35
70
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
Auto.
typ.(2)
—
—
—
20
25
—
—
—
—
20
25
70
—
—
—
15
20
70
mA
4
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
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Rev. B
06/03/08
7
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol
tRC
tAA
tOHA
tACE
tDOE
tHZOE(2)
tLZOE(2)
tHZCE(2
tLZCE(2)
tPU
tPD
Parameter
-10
Min. Max.
Min.
Max.
Unit
Read Cycle Time
8
—
10
—
ns
Address Access Time
—
8
—
10
ns
Output Hold Time
2
—
2
—
ns
CE Access Time
—
8
—
10
ns
OE Access Time
—
5.5
—
6.5
ns
OE to High-Z Output
—
3
—
4
ns
OE to Low-Z Output
0
—
0
—
ns
CE to High-Z Output
0
3
0
4
ns
CE to Low-Z Output
3
—
3
—
ns
Power Up Time
0
—
0
—
ns
Power Down Time
—
8
—
10
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading
specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
-20 ns
Min.
Max.
Unit
tRC
Read Cycle Time
20
—
ns
tAA
Address Access Time
—
20
ns
tOHA
Output Hold Time
2.5
—
ns
tACE
CE Access Time
—
20
ns
tDOE
OE Access Time
—
8
ns
tHZOE(2)
OE to High-Z Output
0
8
ns
tLZOE
OE to Low-Z Output
0
—
ns
(2
tHZCE
CE to High-Z Output
0
8
ns
(2)
tLZCE
CE to Low-Z Output
3
—
ns
tPU
Power Up Time
0
—
ns
tPD
Power Down Time
—
20
ns
(2)
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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Rev. B
06/03/08
9
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
CE
t LZOE
t ACE
t HZCE
t LZCE
DOUT
HIGH-Z
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
10
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Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
Symbol
Parameter
-10
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
8
—
10
—
ns
tSCE
CE to Write End
6.5
—
8
—
ns
tAW
Address Setup Time
to Write End
6.5
—
8
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWE1
WE Pulse Width (OE = HIGH)
6.5
—
8
—
ns
tPWE2
WE Pulse Width (OE = LOW)
8.0
—
10
—
ns
tSD
Data Setup to Write End
5
—
6
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
(2)
tHZWE
WE LOW to High-Z Output
—
3.5
—
5
ns
(2)
tLZWE
WE HIGH to Low-Z Output
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write. Shaded area product in development
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Rev. B
06/03/08
11
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
Parameter
-20 ns
Min. Max.
Unit
tWC
Write Cycle Time
20
—
ns
tSCE
CE to Write End
12
—
ns
tAW
Address Setup Time
to Write End
12
—
ns
tHA
Address Hold from Write End
0
—
ns
tSA
Address Setup Time
0
—
ns
tPWE1
WE Pulse Width (OE = HIGH)
12
—
ns
tPWE2
WE Pulse Width (OE = LOW)
17
—
ns
tSD
Data Setup to Write End
9
—
ns
tHD
Data Hold from Write End
0
—
ns
(3)
tHZWE
WE LOW to High-Z Output
—
9
ns
tLZWE(3)
WE HIGH to Low-Z Output
3
—
ns
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V,
input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input
Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
12
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Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
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Rev. B
06/03/08
13
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
AC WAVEFORMS
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
14
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Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
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Rev. B
06/03/08
15
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VDR
VDD for Data Retention
See Data Retention Waveform
1.2
3.6
V
IDR
Data Retention Current
VDD = 1.2V, CE ≥ VDD – 0.2V
—
—
25
70
4
mA
tSDR
tRDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
Recovery Time
See Data Retention Waveform
tRC
—
ns
Ind.
Auto.
typ.(1)
Note:
1. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE
GND
16
CE ≥ VDD - 0.2V
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Rev. B
06/03/08
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
1
10 (8 )
Order Part No.
Package
IS61WV10248BLL-10MI
IS61WV10248BLL-10MLI
IS61WV10248BLL-10TI
IS61WV10248BLL-10TLI
48 mini BGA (9mm x 11mm)
48 mini BGA (9mm x 11mm), Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.3V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns)
20
Order Part No.
Package
IS61WV10248ALL-20MI
IS61WV10248ALL-20TI
48 mini BGA (9mm x 11mm)
TSOP (Type II)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
10
Order Part No.
Package
IS64WV10248BLL-10MA3
IS64WV10248BLL-10TA3
IS64WV10248BLL-10CTLA3
48 mini BGA (9mm x 11mm)
TSOP (Type II)
TSOP (Type II), Lead-free,
Copper Leadframe
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/08
17
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: M (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
A
D
5
4
3
2
1
A
e
B
B
C
C
D
D
D1
E
E
F
F
G
G
H
H
e
E
E1
A2
A
SEATING PLANE
Notes:
1. Controlling dimensions are in millimeters.
A1
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: M (48-pin)
mBGA - 6mm x 8mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
—
—
1.20
.—
— 0.047
A1
0.25
—
0.40
0.010
— 0.016
A2
0.60
—
—
0.024
—
D
7.90
8.00
8.10
D1
E
0.311 0.314 0.319
5.60BSC
5.90
—
0.220BSC
6.00
6.10
0.232 0.236 0.240
E1
4.00BSC
0.157BSC
e
0.80BSC
0.031BSC
b
0.40 0.45
0.50
0.016 0.018 0.020
mBGA - 7.2mm x 8.7mm
mBGA - 9mm x 11mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
—
—
1.20
—
—
0.047
A
A1
0 .24
—
0.30
0.009
—
0.012
A1
A2
0.60
—
—
0.024
—
—
A2
D
8.60
8.70
8.80
0.339 0.343 0.346
D
10.90 11.00 11.10
0.429 0.433 0.437
5.25BSC
0.207BSC
7.30
0.280 0.283 0.287
E
D1
E
5.25BSC
7.10
7.20
0.207BSC
—
—
1.20
—
0.24
—
0.30
0.60
—
—
D1
8.90
9.00
9.10
—
0.047
0.009
—
0.012
0.024
—
—
0.350 0.354 0.358
E1
3.75BSC
0.148BSC
E1
3.75BSC
0.148BSC
e
0.75BSC
0.030BSC
e
0.75BSC
0.030BSC
0.012 0.014 0.016
b
b
2
0.30 0.35
0.40
0.30
0.35
0.40
0.012 0.014 0.016
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1
1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
E
N/2
D
SEATING PLANE
A
ZD
.
b
e
Symbol
Ref. Std.
No. Leads
A
A1
b
C
D
E1
E
e
L
ZD
α
Millimeters
Min
Max
Inches
Min
Max
(N)
32
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.52
0.012 0.020
0.12 0.21
0.005 0.008
20.82 21.08
0.820 0.830
10.03 10.29
0.391 0.400
11.56 11.96
0.451 0.466
1.27 BSC
0.050 BSC
0.40 0.60
0.016 0.024
0.95 REF
0.037 REF
0°
5°
0°
5°
L
α
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min Max
44
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.45
0.012 0.018
0.12 0.21
0.005 0.008
18.31 18.52
0.721 0.729
10.03 10.29
0.395 0.405
11.56 11.96
0.455 0.471
0.80 BSC
0.032 BSC
0.41 0.60
0.016 0.024
0.81 REF
0.032 REF
0°
5°
0°
5°
Millimeters
Min
Max
C
Inches
Min
Max
50
—
1.20
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
0.88 REF
0°
5°
—
0.047
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
0.035 REF
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
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