ISSI IS61WV6416BLL-12BI 64k x 16 high-speed cmos static ram Datasheet

IS64WV6416BLL
IS61WV6416BLL
ISSI
®
64K x 16 HIGH-SPEED CMOS STATIC RAM
NOVEMBER 2005
FEATURES
• High-speed access time:
12 ns: 3.3V + 10%
15 ns: 2.5V-3.6V
• CMOS low power operation:
50 mW (typical) operating
25 µW (typical) standby
• TTL compatible interface levels
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Automotive Temperature Available
• Lead-free available
DESCRIPTION
The ISSI IS61/64WV6416BLL is a high-speed, 1,048,576bit static RAM organized as 65,536 words by 16 bits. It is
fabricated using ISSI 's high-performance CMOS
technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as
fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low
power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61/64WV6416BLL is packaged in the JEDEC standard 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
CONTROL
CIRCUIT
LB
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/08/05
1
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
PIN CONFIGURATIONS
44-Pin TSOP-II
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
NC
A7
I/O3
VDD
E
VDD
I/O12
NC
NC
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
PIN DESCRIPTIONS
2
A0-A15
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/08/05
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
WE
CE
OE
LB
UB
X
H
X
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
X
X
X
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
VDD Current
ISB1, ISB2
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
VDD
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
VDD Related to GND
Value
–0.5 to VDD+0.5
–65 to +150
1.5
-0.2 to +3.9
Unit
V
°C
W
V
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE (VDD)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
VDD (15 ns)
2.5V-3.6V
2.5V-3.6V
2.5V-3.6V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/08/05
VDD (12 ns)
3.3V + 10%
3.3V + 10%
3.3V + 10%
3
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.5V-3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VDD = Min., IOH = –1.0 mA
2.3
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 1.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VDD + 0.3
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–2
2
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–2
2
µA
Min.
Max.
Unit
Note:
1.
VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 10%
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2
VDD + 0.3
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–2
2
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–2
2
µA
Note:
1.
4
VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
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Rev. B
11/08/05
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Options
ICC
VDD = Max.,
IOUT = 0 mA, f = fMAX
COM.
VDD Dynamic Operating
Supply Current
IND.
AUTO
typ.(2)
ICC1
Operating Supply
Current
VDD = Max.,
Iout = 0mA, f = 0
COM.
IND.
AUTO
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
COM.
IND.
AUTO
typ.(2)
-12 ns
Min. Max.
-15 ns
Min. Max.
Unit
—
—
—
—
35
45
60
20
—
—
—
—
30
40
50
20
mA
—
—
—
5
5
5
—
—
—
5
5
5
mA
—
—
—
—
20
50
75
6
—
—
—
—
20
50
75
6
uA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=2.5V, TA=25oC. Not 100% tested.
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
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Rev. B
11/08/05
5
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
(2.5V-3.6V)
0V to VDD V
1.5ns
VDD/2
Unit
(3.3V + 10%)
0V to VDD V
1.5ns
VDD/2 + 0.05
See Figures 1a and 1b
See Figures 1a and 1b
AC TEST LOADS
319 Ω
Zo=50Ω
2.5V
50Ω
VRef
OUTPUT
30 pF
Including
jig and
scope
Figure 1a.
6
OUTPUT
5 pF
Including
jig and
scope
353 Ω
Figure 1b.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/08/05
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
-12 ns
Min. Max.
-15 ns
Min. Max.
Unit
tRC
Read Cycle Time
12
—
15
—
ns
tAA
Address Access Time
—
12
—
15
ns
tOHA
Output Hold Time
3
—
3
—
ns
tACE
CE Access Time
—
12
—
15
ns
OE Access Time
—
6
—
7
ns
tHZOE
OE to High-Z Output
—
6
0
6
ns
tLZOE(2)
OE to Low-Z Output
0
—
0
—
ns
(2
tHZCE
CE to High-Z Output
0
6
0
6
ns
(2)
tLZCE
CE to Low-Z Output
3
—
3
—
ns
tBA
LB, UB Access Time
—
6
—
7
ns
tHZB
LB, UB to High-Z Output
0
6
0
6
ns
tLZB
LB, UB to Low-Z Output
0
—
0
—
ns
tDOE
(2)
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0V to
VDD V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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Rev. B
11/08/05
7
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
CE
tLZOE
tACE
tHZCE
tBA
tHZB
tLZCE
LB, UB
DOUT
HIGH-Z
tLZB
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
8
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Rev. B
11/08/05
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
Parameter
-12 ns
Min. Max.
-15 ns
Min. Max.
Unit
tWC
Write Cycle Time
12
—
15
—
ns
tSCE
CE to Write End
9
—
10
—
ns
tAW
Address Setup Time
to Write End
9
—
10
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
9
—
10
—
ns
tPWE1
WE Pulse Width (OE = HIGH)
9
—
10
—
ns
tPWE2
WE Pulse Width (OE = LOW)
11
—
12
—
ns
tSD
Data Setup to Write End
9
—
9
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE(3)
WE LOW to High-Z Output
—
6
—
7
ns
tLZWE(3)
WE HIGH to Low-Z Output
3
—
3
—
ns
Notes:
1. Test conditions for IS61WV6416BLL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input
pulse levels of 0V to VDD V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
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Rev. B
11/08/05
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IS64WV6416BLL
IS61WV6416BLL
ISSI
®
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
10
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Rev. B
11/08/05
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR3.eps
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Rev. B
11/08/05
11
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
12
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Rev. B
11/08/05
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Operations
VDR
VDD for Data Retention
See Data Retention Waveform
IDR
Data Retention Current
VDD = 1.8V, CE ≥ VDD – 0.2V
COM.
IND.
AUTO
tSDR
tRDR
Min.
Typ.(1)
Max.
1.8
—
3.6
V
—
—
—
6
6
6
20
50
75
µA
Unit
Data Retention Setup Time
See Data Retention Waveform
0
—
—
ns
Recovery Time
See Data Retention Waveform
tRC
—
—
ns
Note:
1. Typical values are measured at VDD = 2.5V, TA = 25 C. Not 100% tested.
O
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE
GND
CE ≥ VDD - 0.2V
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Rev. B
11/08/05
13
IS64WV6416BLL
IS61WV6416BLL
ISSI
®
ORDERING INFORMATION
Industrial Temperature Range: –40°C to +85°C
Speed (ns)
12
12
12
12
Order Part No.
Package
IS61WV6416BLL-12TI
IS61WV6416BLL-12TLI
IS61WV6416BLL-12BI
IS61WV6416BLL-12BLI
Plastic TSOP
Plastic TSOP, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Temperature Range (A3): –40°C to +125°C
Speed (ns)
1
15 (12 )
15 (121)
15 (121)
15 (121)
Order Part No.
Package
IS64WV6416BLL-15TA3
IS64WV6416BLL-15TLA3
IS64WV6416BLL-15BA3
IS64WV6416BLL-15BLA3
Plastic TSOP
Plastic TSOP, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Note:
1. Speed = 12ns for VDD = 3.3V + 10%. Speed = 15ns for VDD = 2.5V- 3.6V.
14
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Rev. B
11/08/05
ISSI
®
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
A
4
3
2
1
A
e
B
B
C
C
D
D
D
5
D1
E
E
F
F
G
G
H
H
e
E
E1
A2
Notes:
1. Controlling dimensions are in millimeters.
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
MILLIMETER
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
Sym.
Min. Typ. Max.
N0.
Leads
48
INCHES
Min. Typ. Max.
A
—
—
1.20
—
—
0.047
A
—
—
1.20
—
—
0.047
A1
0.24
—
0.30
0.009
—
0.012
A1
0.24
—
0.30
0.009
—
0.012
A2
0.60
—
—
0.024
—
—
A2
0.60
—
—
0.024
—
—
D
7.90
—
8.10
0.311
—
0.319
D
9.90
—
10.10
0.390
—
0.398
D1
E
5.25 BSC
5.90
—
6.10
0.207 BSC
0.232
—
0.240
D1
E
5.25 BSC
7.90
—
0.207 BSC
8.10
0.311
—
0.319
E1
3.75 BSC
0.148 BSC
E1
3.75 BSC
0.148 BSC
e
0.75 BSC
0.030 BSC
e
0.75 BSC
0.030 BSC
0.012 0.014 0.016
b
b
0.30 0.35
0.40
0.30
0.35
0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
ISSI
®
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1
1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
E
N/2
D
SEATING PLANE
A
ZD
.
b
e
Symbol
Ref. Std.
No. Leads
A
A1
b
C
D
E1
E
e
L
ZD
α
Millimeters
Min
Max
Inches
Min
Max
(N)
32
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.52
0.012 0.020
0.12 0.21
0.005 0.008
20.82 21.08
0.820 0.830
10.03 10.29
0.391 0.400
11.56 11.96
0.451 0.466
1.27 BSC
0.050 BSC
0.40 0.60
0.016 0.024
0.95 REF
0.037 REF
0°
5°
0°
5°
L
α
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min Max
44
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.45
0.012 0.018
0.12 0.21
0.005 0.008
18.31 18.52
0.721 0.729
10.03 10.29
0.395 0.405
11.56 11.96
0.455 0.471
0.80 BSC
0.032 BSC
0.41 0.60
0.016 0.024
0.81 REF
0.032 REF
0°
5°
0°
5°
Millimeters
Min
Max
C
Inches
Min
Max
50
—
1.20
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
0.88 REF
0°
5°
—
0.047
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
0.035 REF
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
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