ISSI IS62/65WV2568DALL 256k x 8 low voltage, ultra low power cmos static ram Datasheet

IS62/65WV2568DALL
IS62/65WV2568DBLL
256K x 8 LOW VOLTAGE,
FEBRUARY 2012
ULTRA LOW POWER CMOS STATIC RAM FEATURES
• High-speed access time: 35ns, 45ns, 55ns
DESCRIPTION
The ISSI IS62/65WV2568DALL and IS62/65WV2568DBLL
are high-speed, 2M bit static RAMs organized as
256K words by 8 bits. It is fabricated using ISSI's highperformance CMOS technology.This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply – 1.8V ± 10% Vcc (IS62/65WV2568DALL)
– 2.5V–3.6V Vcc (IS62/65WV2568DBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
When CS1 is HIGH (deselected) or when CS2 is low
(deselected) , the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65WV2568DALL and IS62/65WV2568DBLL are
packaged in the JEDEC standard 32-pin TSOP (TYPE I),
sTSOP (TYPE I), and 36-pin mini BGA.
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/09/2012
1
IS62/65WV2568DALL, IS62/65WV2568DBLL
PIN DESCRIPTIONS
A0-A17 Address Inputs
CS1
Chip Enable 1 Input
CS2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7 Input/Output
NC
No Connection
Vcc
Power
GND
Ground
PIN CONFIGURATION
36-pin mini BGA (B) (6mm x 8mm)
1
2
2
3
4
5
32-pin TSOP (TYPE I), sTSOP (TYPE I)
6
A
A0
A1
CS2
A3
A6
A8
B
I/O4
A2
WE
A4
A7
I/O0
C
I/O5
NC
A5
D
GND
Vcc
E
Vcc
GND
F
I/O6
G
I/O7
H
A9
I/O1
NC
A17
I/O2
OE
CS1
A16
A15
I/O3
A10
A11
A12
A13
A14
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
IS62/65WV2568DALL, IS62/65WV2568DBLL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Tstg
Pt
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Value
–0.2 to Vcc+0.3
–65 to +150
1.0
Unit
V
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE (Vcc)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive (A3)
–40°C to +125°C
IS62/65WV2568DALL
1.8V ± 10%
1.8V ± 10%
1.8V ± 10%
IS62/65WV2568DBLL
2.5V - 3.6V
2.5V - 3.6V
2.5V - 3.6V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Voh
Parameter
Output HIGH Voltage
Vol
Output LOW Voltage
Test Conditions
Ioh = -0.1 mA
Ioh = -1 mA
Iol = 0.1 mA
Iol = 2.1 mA
Vih
Input HIGH Voltage
Vil(1)
Input LOW Voltage
Ili
Ilo
Input Leakage
Output Leakage
Vcc
1.8V ± 10%
2.5-3.6V
1.8V ± 10%
2.5-3.6V
1.8V ± 10%
2.5-3.6V
1.8V ± 10%
2.5-3.6V
GND ≤ Vin ≤ Vcc
GND ≤ Vout ≤ Vcc, Outputs Disabled
Min.
1.4
2.2
—
—
1.4
2.2
–0.2
–0.2
–1
–1
Max.
—
—
0.2
0.4
Vcc + 0.2
Vcc + 0.3
0.4
0.6
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
For IS62/65WV2568DALL:
Vil (min.) = -1.0V AC (pluse width < 10ns). Not 100% tested.
Vih (max.) = Vcc + 1.0V AC; (pluse width < 10ns). Not 100% tested.
For IS62/65WV2568DBLL:
Vil (min.) = -2.0V AC (pluse width < 10ns). Not 100% tested.
Vih (max.) = Vcc + 2.0V AC; (pluse width < 10ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
3
IS62/65WV2568DALL, IS62/65WV2568DBLL
CAPACITANCE(1)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
8
10
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
R1(Ω)
R2(Ω)
Vref
Vtm
62WV2568DALL
(Unit)
0.4V to Vcc-0.2V
5 ns
1.8V ± 10% 3070
3150
0.9V
1.8V
62WV2568DBLL
(Unit)
0.4V to Vcc-0.3V
5ns
Vref
Vref
See Figures 1 and 2
See Figures 1 and 2
2.5V - 3.6V
3070
3150
1.5V
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
4
5 pF
Including
jig and
scope
R2
R2
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
IS62/65WV2568DALL, IS62/65WV2568DBLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Icc
Vcc Dynamic Operating Vcc = Max.,
Com.
Supply Current
Iout = 0 mA, f = fmax
Ind.
Auto.
typ.(2)
Isb1
TTL Standby Current
Vcc = Max.,
Com.
(TTL Inputs)
Vin = Vih or Vil
Ind.
CS1 = Vih , CS2 = Vil, Auto.
f = 1 MHz
Isb2
CMOS Standby
Current (CMOS Inputs)
Vcc = Max.,
CS1 ≥ Vcc – 0.2V,
CS2 ≤ 0.2V,
Vin ≥ Vcc – 0.2V, or
Vin ≤ 0.2V, f = 0
Com.
Ind.
Auto.
typ.(2)
Max.
35ns
15
20
25
10
0.1
0.1
0.2
Max.
45ns
12
15
20
8
0.1
0.1
0.2
Max.
55ns
10
12
15
6
0.1
0.1
0.2
Unit
7
10
–
7
10
18
3
7
10
18
µA
mA
mA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vcc = 3.0V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
5
IS62/65WV2568DALL, IS62/65WV2568DBLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
35ns
45ns
55ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
trc
Read Cycle Time
35
—
45
—
55
—
ns
taa
Address Access Time
—
35
—
45
—
55
ns
toha
Output Hold Time
10
—
10
—
10
—
ns
tacs1/tacs2
CS1/CS2 Access Time
—
35
—
45
—
55
ns
tdoe
OE Access Time
—
15
—
20
—
25
ns
thzoe(2)
OE to High-Z Output
—
10
—
15
—
20
ns
tlzoe(2)
OE to Low-Z Output
5
—
5
—
5
—
ns
thzcs1/thzcs2(2)
CS1/CS2 to High-Z Output
0
10
0
15
0
20
ns
tlzcs1/tlzcs2
CS1/CS2 to Low-Z Output
10
—
10
—
10
—
ns
(2)
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih)
tRC
ADDRESS
tAA
tOHA
DOUT
6
PREVIOUS DATA VALID
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
IS62/65WV2568DALL, IS62/65WV2568DBLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACS1/tACS2
CS2
DOUT
tLZCS1/
tLZCS2
HIGH-Z
tHZCS
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= Vil. CS2=WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
7
IS62/65WV2568DALL, IS62/65WV2568DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
35ns
Symbol
Parameter
twc
45ns
55ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
35
—
45
—
55
—
ns
tscs1/tscs2
CS1/CS2 to Write End
25
—
35
—
45
—
ns
taw
Address Setup Time to Write End
25
—
35
—
45
—
ns
tha
Address Hold from Write End
0
—
0
—
0
—
ns
tsa
Addrress Setup Time
0
—
0
—
0
—
ns
tpwe
WE Pulse Width
30
—
35
—
40
—
ns
tsd
Data Setup to Write End
15
—
20
—
25
—
ns
thd
Data Hold from Write End
0
—
0
—
0
—
ns
thzwe
WE LOW to High-Z Output
—
20
—
20
—
20
ns
tlzwe
WE HIGH to Low-Z Output
5
—
5
—
5
—
ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
8
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
IS62/65WV2568DALL, IS62/65WV2568DBLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
tHD
DATA-IN VALID
9
IS62/65WV2568DALL, IS62/65WV2568DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Vdr
Idr
Parameter
Vcc for Data Retention
Data Retention Current
tsdr
trdr
Data Retention Setup Time
Recovery Time
Test Condition Min.
See Data Retention Waveform
1.5
Vcc = 1.5V, CS1 ≥ Vcc – 0.2V,
Com.
—
CS2 ≤ 0.2V
Ind.
—
Auto.
—
typ.(1)
—
See Data Retention Waveform
0
See Data Retention Waveform
trc
Max.
3.6
7
10
15
2
—
—
Unit
V
µA
ns
ns
Note:
1. Typical values are measured at Vcc = Vdr(min), Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
Data Retention Mode
tSDR
3.0V
2.2V
tRDR
VCC
VDR
CS1 ≥ VCC
CS1
GND
- 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
3.0
VCC
CS2
2.2V
tSDR
tRDR
VDR
0.4V
CS2 ≤ 0.2V
GND
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
IS62/65WV2568DALL, IS62/65WV2568DBLL
ORDERING INFORMATION
IS62WV2568DALL (1.8 ± 10%)
Industrial Range: –40°C to +85°C
Speed (ns)
55
55
55
55
55
55
Order Part No.
IS62WV2568DALL-55TI
IS62WV2568DALL-55TLI
IS62WV2568DALL-55BI
IS62WV2568DALL-55BLI
IS62WV2568DALL-55HI
IS62WV2568DALL-55HLI
Package
TSOP, TYPE I
TSOP, TYPE I, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
sTSOP, TYPE I
sTSOP, TYPE I, Lead-free
IS62WV2568DBLL (2.5V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
35
35
45
45
45
45
45
45
Order Part No.
IS62WV2568DBLL-35HLI
IS62WV2568DBLL-35TLI
IS62WV2568DBLL-45TI
IS62WV2568DBLL-45TLI
IS62WV2568DBLL-45BI
IS62WV2568DBLL-45BLI
IS62WV2568DBLL-45HI
IS62WV2568DBLL-45HLI
Package
sTSOP, TYPE I
TSOP, TYPE I, Lead-free
TSOP, TYPE I
TSOP, TYPE I, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
sTSOP, TYPE I
sTSOP, TYPE I, Lead-free
IS65WV2568DBLL (2.5V - 3.6V)
Automotive Range (A3): –40°C to +125°C
Speed (ns)
45
45
Order Part No.
IS65WV2568DBLL-45TLA3
IS65WV2568DBLL-45HLA3
Package
TSOP, TYPE I, Lead-free
sTSOP, TYPE I, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
11
IS62/65WV2568DALL, IS62/65WV2568DBLL
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
IS62/65WV2568DALL, IS62/65WV2568DBLL
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
13
14
08/12/2008
Package Outline
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS62/65WV2568DALL, IS62/65WV2568DBLL
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/09/2012
Similar pages