ISG4042-T 5 V CATV MODEM RF TUNER AND TRANSMITTER FEATURES DESCRIPTION AND APPLICATIONS TWO WAY DOCSIS BASED DESIGN: 91-857 MHz Downstream 5-42 MHz Upstream The ISG4042-T is an RF tuner/transmitter designed for use in DOCSIS cable modem applications. It is a complete solution that interfaces directly with QAM Mod/Demod IC's. The tuner/ transmitter integrates a diplex filter, dual conversion receiver, transmit AGC amplifier, and other RF filtering (see Figure 1). The diplex filter provides over 40 dB of isolation between the TX band and the RX band. The receiver channel selects and converts QAM signals in the RX band down to the IF sampling frequency. It also provides the necessary gain control to adjust the input power to the DSP chip. The RF transmitter section provides > 56 dB of digitally controlled range while maintaining excellent linearity performance. SINGLE SUPPLY 5 V OPERATION: With Built in Linear Regulation SINGLE AGC CONTROL Simplifies Modem Calibration ULTRA SMALL SIZE: 1.9 x 2.0 x 0.5 in., 1.9 in3 46.2 x 49.0 x 12.5 mm., 28.5 cc. DIGITAL LINEAR RF TRANSMITTER: All Harmonics meets DOCSIS @ 58 dBmV (see note 2) > 56 dB Gain Range (0.5 dB steps) INTERFACES DIRECTLY WITH QAM MOD/DEMOD IC's: (see note 3) ELECTRICAL CHARACTERISTICS (VCC = 5 V, ±2 %, TA = 25°C) (see note 4) SYMBOLS PARAMETERS UNITS MIN MHz dBmV dB dB V dB dBc/Hz dBm kHz msec. ohms dB MHz MHz dB dB ns dBc dBc kHz VPP KΩ 91 -15 TYP MAX RF Performance (RX) fOP VAGC NFMAX RLIN Operating Frequency Range (Center to Center) Input Signal Level Maximum Voltage Gain Automatic Voltage Gain Control Range IF Automatic Voltage Gain Control Noise Figure (at Max Voltage Gain) Phase Noise at 10 kHz Offset LO Radiation at RF Input Resolution Lock Time (end to end channel) Input Impedance (Nominal) Input Return Loss Channel Bandwidth USA Output Frequency Passband Ripple over 5.36 MHz Bandwidth Image Rejection Inband Group Delay CSO1 CTB1 Output Frequency Offset Output IF Voltage Level Output IF Load 857 15 57 45 0 3.3 10 -82 8 -85 -40 31.25 18 75 6 6 43.75 1 2 50 100 45 45 -35 50 50 +35 1 1 Notes: 1. 110 Channels at +15 dBmV/tone. 2. 160K Symbol rate; under DOCSIS PHY - 17 high condition. 3. Application specification for TI 4040/4042. 4. Specifications apply to test conditions listed. * PHY 7/17/18 Data available upon request. Performance tests and ratings for Sirenza Microdevices products were performed internally by Sirenza and measured using specific computer systems and/or components and reflect the approximate performance of the products as measured by those tests. Any difference in circuit implementation, test software, or test equipment may affect actual performance. The information provided herein is believed to be reliable at press time and Sirenza Microdevices assumes no responsibility for the use of this information. All such use shall be entirely at the users own risk. Prices and specifications for Sirenza Microdevices products are subject to change without notice. Buyers should consult Sirenza Microdevices standard terms and conditions of sale for Sirenzas limited warranty with regard to its products. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any product for use in lifesupport devices and/or systems. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 1 www.sirenza.com 4/1/2005 REV. F ISG4042-T ELECTRICAL CHARACTERISTICS (VCC = 5 V, ±2%, TA = 25°C) (see note 2) SYMBOLS PARAMETERS RF Performance (TX) Operating Frequency Range fOP GMAX (Gain Word = 255) GMIN (Gain Word =48) Output Step Size Flatness (5 to 42 MHz) Amplitude Ripple Over 1.28 MHz 2nd Harmonic Level (FIN = 65 MHz, POUT = +58 dBmV)1 3rd Harmonic Level (FIN = 65 MHz, POUT = +58 dBmV)1 Input Impedance Output Return Loss RLOUT TX ON/OFF On/Off Setting Time Group Delay (5-42 MHz) TX Transient Spurs TX Transient Duration Power Requirements Supply Voltage V1 RX Supply Voltage V1 TX Supply Ripple Voltage V1 RX Supply Current ICC1 (RX) ICC1 (TX) Supply Current 1 (RX) Supply Current 1 (TX) TXEN = High Supply Current 1 (TX) TXEN = Low Physical Interface To the CATV Network UNITS MIN MHz dB dB dB dB dB dBmV dBmV Ω dB µs ns mV µs 5 26 V V mV 4.75 4.75 mA mA mA TYP MAX 42 27 -27 0.5 1.7 -26 2.5 0.6 -45 -45 -48 -48 300 6 3.2 5 100 7 5 3.2 5 5 5.25 5.25 100 310 120 8 150 12 Female F-Connector 16 Pin Header To the Motherboard Notes: 1. 160K Symbol rate; under DOCSIS PHY - 17 high condition. 2. Specifications apply to test conditions listed. ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) SYMBOLS VIN PARAMETERS RF Input Voltage UNITS RATINGS dBmV 60 +6.5 VCC1 (RX) Supply Voltage (RX) V VCC (TX) Supply Voltage (TX) V +5.5 TOP Operating Temperature °C -40 to 75 TSTG Storage Temperature °C -40 to 75 TSOL Soldering Temperature °C 260 tSOL Soldering Time sec. 4 Note: 1. Operation in excess of any one of these parameters may result in permanent damage. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 2 www.sirenza.com 4/1/2005 REV. F ISG4042-T PIN FUNCTIONS PIN NO. 1 2 3 4 5 6 7 8 9 PIN NAME GND 5V_TX TXEN TXIN+ TXINLD_TX NC 5V_RX IFAGC 10 11 12 13 GND CLOCK DATA LD_RX 14 15 16 GND IFIF+ DESCRIPTION Ground. Provides low inductance to ground plane. Supply pin for the transmitter. Enable pin for the power amplifier. The amplifier is shutdown when this pin is set low. Non-inverted TX input. Inverted TX input. Latch enable pin for the transmitter serial interface. TTL-compatible inputs. No Connection Supply pin for the receiver. The AGC pin is used to adjust gain in the IF amplifier. The pin has a positive gain vs. voltage slope. 45 dB of gain control is available by the varying the voltage from 0 to 3.3 V. Ground. Provides low inductance to ground plane. Clock pin. High impedance CMOS input. Serial data pin. High impedance CMOS input. MSB entered first. Latch enable pin for the dual PLL. High impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 latches determined by the 2 control bits. Ground. Provides low inductance to ground plane. Inverted final IF output. Non-inverted final IF output. FIGURE 1 43.75 MHz 91-857 MHz QAM DEMOD PLL CABLE PLANT Rx REGULATOR DC/DC QAM MOD 5-42 MHz 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 3 www.sirenza.com 4/1/2005 REV. F ISG4042-T APPLICATION INTERFACE CIRCUIT ISG4042/ TEXAS INSTRUMENTS TNET 4042 T1 TNET4042 ISG4042 1 GND VCC + 330µf - 120nH 1NF 0.1µf 2 5V_TX + 330µf - TUN_GND 3 TX_EN (TI Pin 3) IOUT - 75 Ω (TI Pin 6) IOUT + 75 Ω (TI Pin 20) AMP PD 2.7pf 7.5pf 270nH 30pf 24pf 270nH 24pf 270nH 270nH 2.7pf 7.5pf 4 TX_IN+ 30pf 5 TX_IN- 6 LE2 (TI Pin 173) GENP(3) 7 5V_TX VCC 8 5V_RX + -330µf + 330µf - 10uH TUN_GND 24K 9 IF AGC (TI Pin 166) TAGCS 50K 0.01µf 10 GND TUN_GND TUN_GND TUN_GND (TI Pin 168) GENP(1) 11 CLK (TI Pin 167) GENP(0) 12 DATA (TI Pin 172) GENP(2) 13 LD_EN 14 GND TUN_GND (TI Pin 189) VIN- 15 IF_OUT+ (TI Pin 190) VIN+ 16 IF_OUT- 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 4 www.sirenza.com REV. F 12/10/2003 REV. F 4/1/2005 ISG4042-T TYPICAL PERFORMANCE CURVES PASSBAND AMPLITUDE RIPPLE AGC RANGE 70 RES BW 300 KHz VBW 100 KHz SWP 20.0 msec 60 1 dB/div Gain (dB) 50 40 30 20 10 43.75 MHz 0 SPAN 10.00 MHz 0 0.5 1 1.5 2 2.5 3 Volts (V) PHASE NOISE (Broadband) PHASE NOISE (Narrowband) REF = -15.00 dBm REF = -22.00 dBm RES BW 1.0 KHz VBW 1 KHz SWP 275 msec PNOISE @ 10 KHz = 85 dBc/Hz MKR ∆ = -54.71 dB 10 dB/div 10 dB/div RES BW 1.0 KHz VBW 1 KHz SWP 625 msec PNOISE @ 100 KHz = 109 dBc/Hz MKR ∆ = -79.31 dB 43.75 MHz 43.75 MHz SPAN 25 KHz TX DIPLEXER RESPONSE CONVERSION vs. FREQUENCY 40 60 30 59 58 Conversion Gain (dB) 20 10 Gain (dB) SPAN 250 KHz 0 -10 -20 -30 57 25º C 56 55 70º C 54 53 52 -40 51 50 -50 5 15 25 35 45 55 65 75 85 95 105 115 125 80 280 380 480 580 680 780 880 Frequency (MHz) Frequency 303 S. Technology Court, Broomfield, CO 80021 180 303-327-3030 5 www.sirenza.com 4/1/2005 REV. F ISG4042-T OUTLINE DIMENSIONS (Units in mm) Notes: 1. All tolerance ±0.50 mm unless otherwise specified. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 6 www.sirenza.com 4/1/2005 REV. F ISG4042-T PROGRAMMING INFORMATION FOR RX There are four 22-bit words needed to program the RX. PLL2 has the following words. LSB 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A B B B B B B B B B B B 0 MSB 0 R2 0 N2 PLL1 has the following words. LSB 0 1 1 Where N = and 0 N1 (MHz) + 1100 [ Tune Frequency ] 0.25 N – Mod 64 B= 1 MSB 0 R1 [ 64N [ A = N – 64 (B) They should be entered using the serial data input timing diagram below. Serial Data Input Timing DATA N20: MSB (R20: MSB) N19 (R19) N10 (R10) N9 C2 (R9) (R8) (C2) C1: LSB (C1: LSB) CLOCK tCWL LE tCS OR tCH tCWH tES tEW LE Rx Timing Characteristics SYMBOLS PARAMETERS VALUE MIN TYP UNITS MAX VOH High-Level Output Voltage 4.1 V VOL Low-Level Output Voltage tCS Data to Clock Set Up Time 50 ns tCH Data to Clock Hold Time 10 ns tCWH Clock Pulse Width High 50 ns tCWL 0.4 V Clock Pulse Width Low 50 ns tES Clock to Load Enable Set Up Time 50 ns tEW Load Enable Pulse Width 50 ns Notes: 1. Parenthesis data indicates programmable reference divider data. 2. Data shifted into register on clock rising edge. 3. Data is shifted in MSB first. 4. Pin 6 LD_TX held high. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with amplitudes of 2.2 V @ VCC = 2.7 V and 2.6 V @ VCC = 5.5 V. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 7 www.sirenza.com REV. F 4/1/2005 ISG4042-T PROGRAMMING INFORMATION FOR TX Serial Interface The serial interface has an active-low enable (LD_TX) to bracket the data, with data clocked in MSB first on the rising edge of CLK. Data is stored in the storage latch on the rising edge of LD_TX. The serial interface controls the state of the transmitter. Table 1 and 2 show the register format. Serial-interface timing is shown in Figure 2. LD_RX must not be toggled. A G B C F D E LD_TX (Pin 6) CLOCK (Pin 11) DATA (Pin 12) Functional Modes There are three functional modes controlled through the serial interface or external pins (Table 2): transmit mode, transmit disable mode, and software shutdown mode. D7 D6 D5 D4 D2 D1 D0 E. tSCKH F. tSENH G. tDATAH/tDATAL A. tSENS B. tSDAS C. tSDAH D. tSCKL Transmit Mode Transmit mode is the normal active mode. The TXEN pin must be held high in this mode. D3 Figure 2. Serial-Interface Timing Diagram. Tx Timing Characteristics Transmit-Disable Mode When in transmit-disable mode, the power amplifier is completely shut off. This mode is activated by taking TXEN low. This mode is typically used between bursts in TDMA systems. Transients are controlled by the action of the transformer balance. PARAMETER High Power and Low Noise Modes The upstream has two transmit modes, high power (HP) and low noise (LN) Each of these modes is actuated by the high-order bit D7 of the 8 bit programming word. When D7 is a logic 0, LN mode is enabled. SYMBOL MIN TYP MAX UNITS SEN to SCLK Setup Time tSENS 20 ns SEN to SCLK Hold Time tSENH 10 ns SDA to SCLK Setup Time tSDAS 10 ns SDA to SCLK Hold Time tSDAH 20 ns SDA Pulse Width High tDATAH 50 ns SDA Pulse Width Low tDATAL 50 ns SCLK Pulse Width High tSLKH 50 ns SCLK Pulse Width Low tSLKL 50 ns Table 1. Serial-Interface Control Word Each of these modes is characterized by activation of a distinct output stage. In HP mode, the output stage exhibits 15 dB higher gain than LN mode. The lower gain of the LN output stage allows for significantly lower output noise and lower transmit-disable transients. BIT The full range of gain codes (D6-D0) may be used in either mode. For DOCSIS applications, HP mode is recommended for output levels at or above +42 dBmV (D7 = 1, gain code = 87), LN mode when the output level is below +42 dBmV (D7 = 0, gain code = 115). MNEMONIC DESCRIPTION MSB 7 D7 High-power/low-noise mode select 6 D6 Gain Control, Bit 6 5 D5 Gain Control, Bit 5 4 D4 Gain Control, Bit 4 3 D3 Gain Control, Bit 3 2 D2 Gain Control, Bit 2 1 D1 Gain Control, Bit 1 LSB 0 D0 Gain Control, Bit 0 Table 2. Chip-State Control Bits TXEN D7 D6 D5 D4 D3 D2 D1 D0 GAIN STATE (DECIMAL) GAIN (DB) STATES X X X X X X X X X Shutdown Mode 0 X X X X X X X X Transmit-Disable Mode 1 1 X X X X X X X 1 0 X X X X X X X 1 0 0 1 1 0 0 0 0 48 -26 1 0 1 0 1 0 0 0 0 80 -10 1 0 1 1 1 0 0 1 1 115 8 1 1 1 0 1 0 1 1 1 87 9 1 1 1 1 0 1 1 1 0 110 20 1 1 1 1 1 1 1 0 1 125 28 Transmit Mode-Enable Mode, High Power Transmit Mode-Enable Mode, Low Noise * Typical gain at +25 C and VCC = +5 V. O 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 8 www.sirenza.com 4/1/2005 REV. F